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230 lines
8.4 KiB
C
230 lines
8.4 KiB
C
//============================================================================
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// Product: QUTEST port for NUCLEO-C031C6 board
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// Last updated for version 7.3.0
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// Last updated on 2023-08-18
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//
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// Q u a n t u m L e a P s
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// ------------------------
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// Modern Embedded Software
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//
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// Copyright (C) 2005 Quantum Leaps, LLC. <state-machine.com>
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//
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// SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial
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//
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// This software is dual-licensed under the terms of the open source GNU
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// General Public License version 3 (or any later version), or alternatively,
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// under the terms of one of the closed source Quantum Leaps commercial
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// licenses.
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//
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// The terms of the open source GNU General Public License version 3
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// can be found at: <www.gnu.org/licenses/gpl-3.0>
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//
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// The terms of the closed source Quantum Leaps commercial licenses
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// can be found at: <www.state-machine.com/licensing>
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//
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// Redistributions in source code must retain this top-level comment block.
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// Plagiarizing this software to sidestep the license obligations is illegal.
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//
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// Contact information:
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// <www.state-machine.com>
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// <info@state-machine.com>
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//============================================================================
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#ifndef Q_SPY
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#error "Q_SPY must be defined to compile qutest_port.c"
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#endif // Q_SPY
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#define QP_IMPL // this is QP implementation
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#include "qp_port.h" // QP port
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#include "qsafe.h" // QP Functional Safety (FuSa) Subsystem
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#include "qs_port.h" // QS port
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#include "qs_pkg.h" // QS package-scope interface
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#include "stm32c0xx.h" // CMSIS-compliant header file for the MCU used
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// add other drivers if necessary...
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//Q_DEFINE_THIS_MODULE("qutest_port")
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// Local-scope defines -------------------------------------------------------
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// LED pins available on the board (just one user LED LD4--Green on PA.5)
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#define LD4_PIN 5U
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// Button pins available on the board (just one user Button B1 on PC.13)
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#define B1_PIN 13U
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static uint16_t const UARTPrescTable[12] = {
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1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U
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};
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#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
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((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) \
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+ ((__BAUD__)/2U)) / (__BAUD__))
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#define UART_PRESCALER_DIV1 0U
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// USART2 pins PA.2 and PA.3
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#define USART2_TX_PIN 2U
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#define USART2_RX_PIN 3U
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//............................................................................
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// ISR for receiving bytes from the QSPY Back-End
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// NOTE: This ISR is "QF-unaware" meaning that it does not interact with
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// the QF/QK and is not disabled. Such ISRs don't need to call QK_ISR_ENTRY/
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// QK_ISR_EXIT and they cannot post or publish events.
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void USART2_IRQHandler(void); // prototype
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void USART2_IRQHandler(void) { // used in QS-RX (kernel UNAWARE interrupt)
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// is RX register NOT empty?
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while ((USART2->ISR & (1U << 5U)) != 0U) {
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uint32_t b = USART2->RDR;
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QS_RX_PUT(b);
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}
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}
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//............................................................................
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void assert_failed(char const * const module, int_t const id); // prototype
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void assert_failed(char const * const module, int_t const id) {
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Q_onError(module, id);
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}
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// QS callbacks ==============================================================
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uint8_t QS_onStartup(void const *arg) {
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Q_UNUSED_PAR(arg);
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static uint8_t qsTxBuf[2*1024]; // buffer for QS-TX channel
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QS_initBuf (qsTxBuf, sizeof(qsTxBuf));
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static uint8_t qsRxBuf[256]; // buffer for QS-RX channel
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QS_rxInitBuf(qsRxBuf, sizeof(qsRxBuf));
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// NOTE: SystemInit() already called from the startup code
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// but SystemCoreClock needs to be updated
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SystemCoreClockUpdate();
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// enable GPIOA clock port for the LED LD4
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RCC->IOPENR |= (1U << 0U);
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// set all used GPIOA pins as push-pull output, no pull-up, pull-down
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GPIOA->MODER &= ~(3U << 2U*LD4_PIN);
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GPIOA->MODER |= (1U << 2U*LD4_PIN);
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GPIOA->OTYPER &= ~(1U << LD4_PIN);
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GPIOA->OSPEEDR &= ~(3U << 2U*LD4_PIN);
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GPIOA->OSPEEDR |= (1U << 2U*LD4_PIN);
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GPIOA->PUPDR &= ~(3U << 2U*LD4_PIN);
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// enable GPIOC clock port for the Button B1
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RCC->IOPENR |= (1U << 2U);
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// configure Button B1 pin on GPIOC as input, no pull-up, pull-down
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GPIOC->MODER &= ~(3U << 2U*B1_PIN);
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GPIOC->PUPDR &= ~(3U << 2U*B1_PIN);
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// enable peripheral clock for USART2
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RCC->IOPENR |= ( 1U << 0U); // Enable GPIOA clock for USART pins
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RCC->APBENR1 |= ( 1U << 17U); // Enable USART#2 clock
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// Configure PA to USART2_RX, PA to USART2_TX
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GPIOA->AFR[0] &= ~((15U << 4U*USART2_RX_PIN) | (15U << 4U*USART2_TX_PIN));
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GPIOA->AFR[0] |= (( 1U << 4U*USART2_RX_PIN) | ( 1U << 4U*USART2_TX_PIN));
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GPIOA->MODER &= ~(( 3U << 2U*USART2_RX_PIN) | ( 3U << 2U*USART2_TX_PIN));
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GPIOA->MODER |= (( 2U << 2U*USART2_RX_PIN) | ( 2U << 2U*USART2_TX_PIN));
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// baud rate
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USART2->BRR = UART_DIV_SAMPLING16(
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SystemCoreClock, 115200U, UART_PRESCALER_DIV1);
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USART2->CR3 = 0x0000U | // no flow control
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(1U << 12U); // disable overrun detection (OVRDIS)
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USART2->CR2 = 0x0000U; // 1 stop bit
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USART2->CR1 = ((1U << 2U) | // enable RX
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(1U << 3U) | // enable TX
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(1U << 5U) | // enable RX interrupt
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(0U << 12U) | // 8 data bits
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(0U << 28U) | // 8 data bits
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(1U << 0U)); // enable USART
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// explicitly set NVIC priorities of all Cortex-M interrupts used
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NVIC_SetPriorityGrouping(0U);
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NVIC_SetPriority(USART2_IRQn, 0U);
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// enable the UART RX interrupt...
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NVIC_EnableIRQ(USART2_IRQn); // UART2 interrupt used for QS-RX
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return 1U; // return success
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}
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//............................................................................
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void QS_onCleanup(void) {
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// wait as long as the UART is busy
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while ((USART2->ISR & (1U << 7U)) == 0U) {
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}
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// delay before returning to allow all produced QS bytes to be received
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for (uint32_t volatile dly_ctr = 10000U; dly_ctr > 0U; --dly_ctr) {
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}
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}
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//............................................................................
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void QS_onFlush(void) {
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for (;;) {
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QF_INT_DISABLE();
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uint16_t b = QS_getByte();
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QF_INT_ENABLE();
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if (b != QS_EOD) {
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while ((USART2->ISR & (1U << 7U)) == 0U) {
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}
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USART2->TDR = b; // put into the DR register
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}
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else {
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break;
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}
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}
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}
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//............................................................................
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// callback function to reset the target (to be implemented in the BSP)
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void QS_onReset(void) {
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NVIC_SystemReset();
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}
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//............................................................................
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void QS_doOutput(void) {
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if ((USART2->ISR & (1U << 7U)) != 0U) { // is TXE empty?
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QF_INT_DISABLE();
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uint16_t b = QS_getByte();
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QF_INT_ENABLE();
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if (b != QS_EOD) { // not End-Of-Data?
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USART2->TDR = b; // put into the DR register
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}
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}
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}
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//............................................................................
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void QS_onTestLoop() {
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QS_rxPriv_.inTestLoop = true;
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while (QS_rxPriv_.inTestLoop) {
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// toggle an LED LD2 on and then off (not enough LEDs, see NOTE02)
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GPIOA->BSRR = (1U << LD4_PIN); // turn LED[n] on
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GPIOA->BSRR = (1U << (LD4_PIN + 16U)); // turn LED[n] off
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QS_rxParse(); // parse all the received bytes
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if ((USART2->ISR & (1U << 7U)) != 0U) { // is TXE empty?
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QF_INT_DISABLE();
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uint16_t b = QS_getByte();
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QF_INT_ENABLE();
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if (b != QS_EOD) { // not End-Of-Data?
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USART2->TDR = (b & 0xFFU); // put into the DR register
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}
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}
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}
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// set inTestLoop to true in case calls to QS_onTestLoop() nest,
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// which can happen through the calls to QS_TEST_PAUSE().
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QS_rxPriv_.inTestLoop = true;
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}
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//============================================================================
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// NOTE0:
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// ARM Cortex-M0+ does NOT provide "kernel-unaware" interrupts, and
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// consequently *all* interrupts are "kernel-aware". This means that
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// the UART interrupt used for QS-RX is frequently DISABLED (e.g., to
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// perform QS-TX). That can lead to lost some of the received bytes, and
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// consequently some QUTest tests might be failing.
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// A fix for that would be to use DMA for handling QS-RX, but this is
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// currently not implemented.
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//
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