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406 lines
15 KiB
C
406 lines
15 KiB
C
/*****************************************************************************
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* BSP for EK-TM4C123GXL with QP/C framework
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*****************************************************************************/
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#include "qpc.h" /* QP/C API */
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#include "bsp.h"
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#include "TM4C123GH6PM.h" /* the device specific header (TI) */
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/* add other drivers if necessary... */
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/* Local-scope objects -----------------------------------------------------*/
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/* LEDs on the board */
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#define LED_RED (1U << 1)
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#define LED_GREEN (1U << 3)
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#define LED_BLUE (1U << 2)
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/* Buttons on the board */
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#define BTN_SW1 (1U << 4)
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#define BTN_SW2 (1U << 0)
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/* Test pins */
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#define PD0_PIN (1U << 0)
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#define PD1_PIN (1U << 1)
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#ifdef Q_SPY
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#define UART_BAUD_RATE 115200U
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#define UART_FR_TXFE (1U << 7)
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#define UART_FR_RXFE (1U << 4)
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#define UART_TXFIFO_DEPTH 16U
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#endif
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/* Assertion handler ======================================================*/
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Q_NORETURN Q_onAssert(char const * module, int_t id) {
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/* TBD: Perform corrective actions and damage control
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* SPECIFIC to your particular system.
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*/
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(void)module; /* unused parameter */
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(void)id; /* unused parameter */
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GPIOF_AHB->DATA_Bits[LED_RED | LED_GREEN | LED_BLUE] = 0xFFU; /* all ON */
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#ifndef NDEBUG /* debug build? */
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while (1) { /* tie the CPU in this endless loop */
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}
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#endif
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NVIC_SystemReset(); /* reset the CPU */
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}
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//............................................................................
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/* assert-handling function called by exception handlers in the startup code */
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void assert_failed(char const * const module, int_t const id); // prototype
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void assert_failed(char const * const module, int_t const id) {
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Q_onAssert(module, id);
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}
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/* ISRs ===============================================*/
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void SysTick_Handler(void) {
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/* state of the button debouncing, see below */
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static struct ButtonsDebouncing {
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uint32_t depressed;
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uint32_t previous;
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} buttons = { 0U, 0U };
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uint32_t current;
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uint32_t tmp;
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GPIOD_AHB->DATA_Bits[PD0_PIN] = PD0_PIN;
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QF_TICK_X(0U, (void *)0); /* process all QP/C time events */
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/* Perform the debouncing of buttons. The algorithm for debouncing
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* adapted from the book "Embedded Systems Dictionary" by Jack Ganssle
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* and Michael Barr, page 71.
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*/
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current = ~GPIOF_AHB->DATA_Bits[BTN_SW1 | BTN_SW2]; /* read SW1 & SW2 */
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tmp = buttons.depressed; /* save the debounced depressed buttons */
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buttons.depressed |= (buttons.previous & current); /* set depressed */
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buttons.depressed &= (buttons.previous | current); /* clear released */
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buttons.previous = current; /* update the history */
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tmp ^= buttons.depressed; /* changed debounced depressed */
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if ((tmp & BTN_SW1) != 0U) { /* debounced SW1 state changed? */
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if ((buttons.depressed & BTN_SW1) != 0U) { /* is SW1 depressed? */
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/* post the "button-pressed" event from ISR */
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static QEvt const buttonPressedEvt
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= QEVT_INITIALIZER(BUTTON_PRESSED_SIG);
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QACTIVE_POST(AO_TimeBomb, &buttonPressedEvt, 0U);
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GPIOD_AHB->DATA_Bits[PD1_PIN] = PD1_PIN;
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QS_BEGIN_ID(QS_USER, 0)
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QS_STR("SW1");
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QS_U8(1U, 1U);
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QS_END()
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GPIOD_AHB->DATA_Bits[PD1_PIN] = 0U;
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}
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else { /* the button is released */
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/* post the "button-released" event from ISR */
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static QEvt const buttonReleasedEvt
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= QEVT_INITIALIZER(BUTTON_RELEASED_SIG);
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QACTIVE_POST(AO_TimeBomb, &buttonReleasedEvt, 0U);
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QS_BEGIN_ID(QS_USER, 0)
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QS_STR("SW1");
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QS_U8(1U, 0U);
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QS_END()
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}
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}
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if ((tmp & BTN_SW2) != 0U) { /* debounced SW2 state changed? */
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if ((buttons.depressed & BTN_SW2) != 0U) { /* is SW2 depressed? */
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/* post the "button-pressed" event from ISR */
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static QEvt const button2PressedEvt
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= QEVT_INITIALIZER(BUTTON2_PRESSED_SIG);
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QACTIVE_POST(AO_TimeBomb, &button2PressedEvt, 0U);
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QS_BEGIN_ID(QS_USER, 0)
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QS_STR("SW2");
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QS_U8(1U, 1U);
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QS_END()
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}
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else { /* the button is released */
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/* post the "button-released" event from ISR */
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static QEvt const button2ReleasedEvt
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= QEVT_INITIALIZER(BUTTON2_RELEASED_SIG);
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QACTIVE_POST(AO_TimeBomb, &button2ReleasedEvt, 0U);
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QS_BEGIN_ID(QS_USER, 0)
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QS_STR("SW2");
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QS_U8(1U, 0U);
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QS_END()
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}
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}
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GPIOD_AHB->DATA_Bits[PD0_PIN] = 0U;
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}
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/*..........................................................................*/
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void QV_onIdle(void) {
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#ifdef Q_SPY
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QF_INT_ENABLE();
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QS_rxParse(); /* parse all the received bytes */
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if ((UART0->FR & UART_FR_TXFE) != 0U) { /* TX done? */
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uint16_t fifo = UART_TXFIFO_DEPTH; /* max bytes we can accept */
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uint8_t const *block;
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QF_INT_DISABLE();
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block = QS_getBlock(&fifo); /* try to get next block to transmit */
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QF_INT_ENABLE();
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while (fifo-- != 0) { /* any bytes in the block? */
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UART0->DR = *block++; /* put into the FIFO */
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}
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}
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#elif defined NDEBUG
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/* Put the CPU and peripherals to the low-power mode.
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* you might need to customize the clock management for your application,
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* see the datasheet for your particular Cortex-M MCU.
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*/
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QV_CPU_SLEEP(); /* atomically go to sleep and enable interrupts */
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#else
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QF_INT_ENABLE(); /* just enable interrupts */
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#endif
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}
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/* BSP functions ===========================================================*/
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void BSP_init(void) {
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/* enable clock for to the peripherals used by this application... */
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SYSCTL->RCGCGPIO |= (1U << 5); /* enable Run mode for GPIOF */
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SYSCTL->RCGCGPIO |= (1U << 3); /* enable Run mode for GPIOD */
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SYSCTL->GPIOHBCTL |= (1U << 5); /* enable AHB for GPIOF */
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SYSCTL->GPIOHBCTL |= (1U << 3); /* enable AHB for GPIOD */
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__ISB();
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__DSB();
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/* configure LEDs (digital output) */
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GPIOF_AHB->DIR |= (LED_RED | LED_BLUE | LED_GREEN);
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GPIOF_AHB->DEN |= (LED_RED | LED_BLUE | LED_GREEN);
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GPIOF_AHB->DATA_Bits[LED_RED | LED_BLUE | LED_GREEN] = 0U;
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/* configure Test pins (digital output) */
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GPIOD_AHB->DIR |= (PD0_PIN | PD1_PIN);
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GPIOD_AHB->DEN |= (PD0_PIN | PD1_PIN);
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/* configure switches... */
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/* unlock access to the SW2 pin because it is PROTECTED */
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GPIOF_AHB->LOCK = 0x4C4F434BU; /* unlock GPIOCR register for SW2 */
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/* commit the write (cast const away) */
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*(uint32_t volatile *)&GPIOF_AHB->CR = 0x01U;
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GPIOF_AHB->DIR &= ~(BTN_SW1 | BTN_SW2); /* input */
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GPIOF_AHB->DEN |= (BTN_SW1 | BTN_SW2); /* digital enable */
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GPIOF_AHB->PUR |= (BTN_SW1 | BTN_SW2); /* pull-up resistor enable */
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*(uint32_t volatile *)&GPIOF_AHB->CR = 0x00U;
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GPIOF_AHB->LOCK = 0x0; /* lock GPIOCR register for SW2 */
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QS_INIT((void *)0); /* initialize the QS software tracing */
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/* setup the QS filters... */
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//QS_GLB_FILTER(QS_UA_RECORDS); /* all User records */
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//QS_GLB_FILTER(QS_SM_RECORDS); /* state machine records */
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QS_GLB_FILTER(QS_ALL_RECORDS); /* all QS records */
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QS_GLB_FILTER(-QS_QF_TICK); /* disable */
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/* prodice the QS dictionaries... */
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QS_OBJ_DICTIONARY(AO_TimeBomb);
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QS_SIG_DICTIONARY(BUTTON_PRESSED_SIG, (void *)0);
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QS_SIG_DICTIONARY(BUTTON_RELEASED_SIG, (void *)0);
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QS_SIG_DICTIONARY(BUTTON2_PRESSED_SIG, (void *)0);
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QS_SIG_DICTIONARY(BUTTON2_RELEASED_SIG, (void *)0);
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QS_SIG_DICTIONARY(TIMEOUT_SIG, (void *)0);
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}
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/*..........................................................................*/
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void QF_onStartup(void) {
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/* NOTE: SystemInit() has been already called from the startup code
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* but SystemCoreClock needs to be updated
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*/
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SystemCoreClockUpdate();
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/* set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate
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* NOTE: do NOT call OS_CPU_SysTickInit() from uC/OS-II
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*/
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SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC);
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/* set priorities of ALL ISRs used in the system, see NOTE1 */
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NVIC_SetPriority(SysTick_IRQn, QF_AWARE_ISR_CMSIS_PRI + 1U);
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/* ... */
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/* enable IRQs in the NVIC... */
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/* ... */
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}
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/*..........................................................................*/
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void QF_onCleanup(void) {
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}
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/*..........................................................................*/
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void BSP_ledRedOn(void) {
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GPIOF_AHB->DATA_Bits[LED_RED] = LED_RED;
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QS_BEGIN_ID(QS_USER, 0)
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QS_STR("red");
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QS_U8(1U, 1U);
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QS_END()
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}
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/*..........................................................................*/
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void BSP_ledRedOff(void) {
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GPIOF_AHB->DATA_Bits[LED_RED] = 0U;
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QS_BEGIN_ID(QS_USER, 0)
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QS_STR("red");
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QS_U8(1U, 0U);
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QS_END()
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}
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/*..........................................................................*/
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void BSP_ledBlueOn(void) {
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GPIOF_AHB->DATA_Bits[LED_BLUE] = LED_BLUE;
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QS_BEGIN_ID(QS_USER, 0)
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QS_STR("blue");
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QS_U8(1U, 1U);
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QS_END()
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}
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/*..........................................................................*/
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void BSP_ledBlueOff(void) {
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GPIOF_AHB->DATA_Bits[LED_BLUE] = 0U;
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QS_BEGIN_ID(QS_USER, 0)
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QS_STR("blue");
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QS_U8(1U, 0U);
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QS_END()
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}
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/*..........................................................................*/
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void BSP_ledGreenOn(void) {
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GPIOF_AHB->DATA_Bits[LED_GREEN] = LED_GREEN;
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QS_BEGIN_ID(QS_USER, 0)
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QS_STR("green");
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QS_U8(1U, 1U);
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QS_END()
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}
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/*..........................................................................*/
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void BSP_ledGreenOff(void) {
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GPIOF_AHB->DATA_Bits[LED_GREEN] = 0U;
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QS_BEGIN_ID(QS_USER, 0)
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QS_STR("green");
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QS_U8(1U, 0U);
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QS_END()
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}
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/* QS callbacks ============================================================*/
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#ifdef Q_SPY
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/*..........................................................................*/
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uint8_t QS_onStartup(void const *arg) {
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Q_UNUSED_PAR(arg);
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static uint8_t qsTxBuf[1000]; /* buffer for QS transmit channel */
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static uint8_t qsRxBuf[100]; /* buffer for QS receive channel */
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QS_initBuf (qsTxBuf, sizeof(qsTxBuf));
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QS_rxInitBuf(qsRxBuf, sizeof(qsRxBuf));
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/* enable clock for UART0 and GPIOA (used by UART0 pins) */
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SYSCTL->RCGCUART |= (1U << 0); /* enable Run mode for UART0 */
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SYSCTL->RCGCGPIO |= (1U << 0); /* enable Run mode for GPIOA */
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/* configure UART0 pins for UART operation */
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uint32_t tmp = (1U << 0) | (1U << 1);
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GPIOA->DIR &= ~tmp;
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GPIOA->SLR &= ~tmp;
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GPIOA->ODR &= ~tmp;
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GPIOA->PUR &= ~tmp;
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GPIOA->PDR &= ~tmp;
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GPIOA->AMSEL &= ~tmp; /* disable analog function on the pins */
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GPIOA->AFSEL |= tmp; /* enable ALT function on the pins */
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GPIOA->DEN |= tmp; /* enable digital I/O on the pins */
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GPIOA->PCTL &= ~0x00U;
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GPIOA->PCTL |= 0x11U;
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/* configure the UART for the desired baud rate, 8-N-1 operation */
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tmp = (((SystemCoreClock * 8U) / UART_BAUD_RATE) + 1U) / 2U;
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UART0->IBRD = tmp / 64U;
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UART0->FBRD = tmp % 64U;
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UART0->LCRH = (0x3U << 5); /* configure 8-N-1 operation */
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UART0->LCRH |= (0x1U << 4); /* enable FIFOs */
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UART0->CTL = (1U << 0) /* UART enable */
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| (1U << 8) /* UART TX enable */
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| (1U << 9); /* UART RX enable */
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/* configure UART interrupts (for the RX channel) */
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UART0->IM |= (1U << 4) | (1U << 6); /* enable RX and RX-TO interrupt */
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UART0->IFLS |= (0x2U << 2); /* interrupt on RX FIFO half-full */
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/* NOTE: do not enable the UART0 interrupt yet. Wait till QF_onStartup() */
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NVIC_SetPriority(UART0_IRQn, 0U); /* kernel unaware interrupt */
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NVIC_EnableIRQ(UART0_IRQn); /* UART0 interrupt used for QS-RX */
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/* configure TIMER5 to produce QS time stamp */
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SYSCTL->RCGCTIMER |= (1U << 5); /* enable run mode for Timer5 */
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TIMER5->CTL = 0U; /* disable Timer1 output */
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TIMER5->CFG = 0x0U; /* 32-bit configuration */
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TIMER5->TAMR = (1U << 4) | 0x02; /* up-counting periodic mode */
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TIMER5->TAILR= 0xFFFFFFFFU; /* timer interval */
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TIMER5->ICR = 0x1U; /* TimerA timeout flag bit clears*/
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TIMER5->CTL |= (1U << 0); /* enable TimerA module */
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return 1U; /* return success */
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}
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/*..........................................................................*/
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void QS_onCleanup(void) {
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}
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/*..........................................................................*/
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QSTimeCtr QS_onGetTime(void) { /* NOTE: invoked with interrupts DISABLED */
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return TIMER5->TAV;
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}
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/*..........................................................................*/
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void QS_onFlush(void) {
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while (true) {
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/* try to get next byte to transmit */
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QF_INT_DISABLE();
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uint16_t b = QS_getByte();
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QF_INT_ENABLE();
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if (b != QS_EOD) { /* NOT end-of-data */
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/* busy-wait as long as TX FIFO has data to transmit */
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while ((UART0->FR & UART_FR_TXFE) == 0) {
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}
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/* place the byte in the UART DR register */
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UART0->DR = b;
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}
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else {
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break; /* break out of the loop */
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}
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}
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}
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/*..........................................................................*/
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/*
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* ISR for receiving bytes from the QSPY Back-End
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* NOTE: This ISR is "QF-unaware" meaning that it does not interact with
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* the QF/QK and is not disabled. Such ISRs don't need to call QK_ISR_ENTRY/
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* QK_ISR_EXIT and they cannot post or publish events.
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*/
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void UART0_IRQHandler(void) {
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uint32_t status = UART0->RIS; /* get the raw interrupt status */
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UART0->ICR = status; /* clear the asserted interrupts */
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while ((UART0->FR & UART_FR_RXFE) == 0) { /* while RX FIFO NOT empty */
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uint32_t b = UART0->DR;
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QS_RX_PUT(b);
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}
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QV_ARM_ERRATUM_838869();
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}
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/*..........................................................................*/
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/*! callback function to reset the target (to be implemented in the BSP) */
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void QS_onReset(void) {
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NVIC_SystemReset();
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}
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/*..........................................................................*/
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/*! callback function to execute a user command (to be implemented in BSP) */
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void QS_onCommand(uint8_t cmdId,
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uint32_t param1, uint32_t param2, uint32_t param3)
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{
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QS_BEGIN_ID(QS_USER + 1U, 0U) /* app-specific record */
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QS_U8(2, cmdId);
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QS_U32(8, param1);
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QS_U32(8, param2);
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QS_U32(8, param3);
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QS_END()
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}
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#endif /* Q_SPY */
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