2.1
### uVision Project, (C) Keil Software
dbg
0x4
ARM-ADS
6220000::V6.22::ARMCLANG
1
STM32C031C6Tx
STMicroelectronics
Keil.STM32C0xx_DFP.1.0.0
https://www.keil.com/pack/
IRAM(0x20000000,0x00003000) IROM(0x08000000,0x00008000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE
UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32C0x_32 -FS08000000 -FL08000 -FP0($$Device:STM32C031C6Tx$CMSIS\Flash\STM32C0x_32.FLM))
0
$$Device:STM32C031C6Tx$Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h
$$Device:STM32C031C6Tx$CMSIS\SVD\STM32C031.svd
0
0
0
0
0
0
1
.\dbg\
lesson
1
0
0
1
1
.\dbg\
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
3
1
SARMCM3.DLL
-REMAP-MPU
DARMCM1.DLL
-pCM0+
SARMCM3.DLL
-MPU
TARMCM1.DLL
-pCM0+
1
0
0
0
16
1
0
0
1
1
-1
1
BIN\UL2CM3.DLL
0
0
1
1
1
1
1
1
1
0
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
"Cortex-M0+"
0
0
0
1
1
0
0
0
0
0
0
0
0
8
0
0
0
0
3
3
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0x0
0x0
0
0x0
0x0
0
0x0
0x0
0
0x0
0x0
0
0x0
0x0
0
0x0
0x0
0
0x20000000
0x3000
1
0x8000000
0x8000
0
0x0
0x0
1
0x0
0x0
1
0x0
0x0
1
0x0
0x0
1
0x8000000
0x8000
1
0x0
0x0
0
0x0
0x0
0
0x0
0x0
0
0x0
0x0
0
0x20000000
0x3000
0
0x0
0x0
1
1
0
0
1
0
0
0
0
0
3
0
0
0
0
0
3
3
1
1
0
0
0
-Wno-declaration-after-statement
.;..\ucos2\Source;..\ucos2\Ports\ARM-Cortex-M\ARMv6-M\ARM;..\nucleo-c031c6;..\CMSIS\Include
1
0
0
0
0
0
0
1
0
3
Stack_Size=2048,Heap_Size=0
0
0
0
0
1
0
0x00000000
0x20000000
lesson.sct
Source
main.c
1
.\main.c
bsp.c
1
.\bsp.c
bsp.h
5
.\bsp.h
uc_ao.c
1
.\uc_ao.c
uc_ao.h
5
.\uc_ao.h
nucleo-c031c6
README.txt
5
..\nucleo-c031c6\README.txt
stm32c0xx.h
5
..\nucleo-c031c6\stm32c0xx.h
stm32c031xx.h
5
..\nucleo-c031c6\stm32c031xx.h
system_stm32c0xx.c
1
..\nucleo-c031c6\system_stm32c0xx.c
system_stm32c0xx.h
5
..\nucleo-c031c6\system_stm32c0xx.h
startup_stm32c031xx.s
2
..\nucleo-c031c6\arm\startup_stm32c031xx.s
CMSIS
cmsis_armclang.h
5
..\CMSIS\Include\cmsis_armclang.h
cmsis_compiler.h
5
..\CMSIS\Include\cmsis_compiler.h
cmsis_version.h
5
..\CMSIS\Include\cmsis_version.h
core_cm0plus.h
5
..\CMSIS\Include\core_cm0plus.h
ucos2
os.h
5
..\ucos2\Source\os.h
os_core.c
1
..\ucos2\Source\os_core.c
os_flag.c
1
..\ucos2\Source\os_flag.c
os_mbox.c
1
..\ucos2\Source\os_mbox.c
os_mem.c
1
..\ucos2\Source\os_mem.c
os_mutex.c
1
..\ucos2\Source\os_mutex.c
os_q.c
1
..\ucos2\Source\os_q.c
os_sem.c
1
..\ucos2\Source\os_sem.c
os_task.c
1
..\ucos2\Source\os_task.c
os_time.c
1
..\ucos2\Source\os_time.c
os_tmr.c
1
..\ucos2\Source\os_tmr.c
ucos2-port
os_cpu_c.c
1
..\ucos2\Ports\ARM-Cortex-M\ARMv6-M\os_cpu_c.c
os_cpu.h
5
..\ucos2\Ports\ARM-Cortex-M\ARMv6-M\ARM\os_cpu.h
os_cpu_a.asm
2
..\ucos2\Ports\ARM-Cortex-M\ARMv6-M\ARM\os_cpu_a.asm
os_dbg.c
1
..\ucos2\Ports\ARM-Cortex-M\ARMv6-M\ARM\os_dbg.c
RTE\Device\TM4C123GH6PM\startup_TM4C123.s
RTE\Device\TM4C123GH6PM\system_TM4C123.c
lesson
1