diff --git a/lesson-01/simulator-iar/project.ewd b/lesson-01/simulator-iar/project.ewd
new file mode 100644
index 0000000..e6a0eaf
--- /dev/null
+++ b/lesson-01/simulator-iar/project.ewd
@@ -0,0 +1,1554 @@
+
+
+ 3
+
+ Debug
+
+ ARM
+
+ 1
+
+ C-SPY
+ 2
+
+ 32
+ 1
+ 1
+
+ CInput
+ 1
+
+
+ CEndian
+ 1
+
+
+ CProcessor
+ 1
+
+
+ OCVariant
+ 0
+
+
+ MacOverride
+ 0
+
+
+ MacFile
+
+
+
+ MemOverride
+ 0
+
+
+ MemFile
+ $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf
+
+
+ RunToEnable
+ 1
+
+
+ RunToName
+ main
+
+
+ CExtraOptionsCheck
+ 0
+
+
+ CExtraOptions
+
+
+
+ CFpuProcessor
+ 1
+
+
+ OCDDFArgumentProducer
+
+
+
+ OCDownloadSuppressDownload
+ 0
+
+
+ OCDownloadVerifyAll
+ 1
+
+
+ OCProductVersion
+ 6.50.2.4581
+
+
+ OCDynDriverList
+ ARMSIM_ID
+
+
+ OCLastSavedByProductVersion
+ 9.32.1.54977
+
+
+ UseFlashLoader
+ 1
+
+
+ CLowLevel
+ 1
+
+
+ OCBE8Slave
+ 1
+
+
+ MacFile2
+
+
+
+ CDevice
+ 1
+
+
+ FlashLoadersV3
+ $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashTC4_H6_o.board
+
+
+ OCImagesSuppressCheck1
+ 0
+
+
+ OCImagesPath1
+
+
+
+ OCImagesSuppressCheck2
+ 0
+
+
+ OCImagesPath2
+
+
+
+ OCImagesSuppressCheck3
+ 0
+
+
+ OCImagesPath3
+
+
+
+ OverrideDefFlashBoard
+ 0
+
+
+ OCImagesOffset1
+
+
+
+ OCImagesOffset2
+
+
+
+ OCImagesOffset3
+
+
+
+ OCImagesUse1
+ 0
+
+
+ OCImagesUse2
+ 0
+
+
+ OCImagesUse3
+ 0
+
+
+ OCDeviceConfigMacroFile
+ 1
+
+
+ OCDebuggerExtraOption
+ 1
+
+
+ OCAllMTBOptions
+ 1
+
+
+ OCMulticoreNrOfCores
+ 1
+
+
+ OCMulticoreWorkspace
+
+
+
+ OCMulticoreSlaveProject
+
+
+
+ OCMulticoreSlaveConfiguration
+
+
+
+ OCDownloadExtraImage
+ 1
+
+
+ OCAttachSlave
+ 0
+
+
+ MassEraseBeforeFlashing
+ 0
+
+
+ OCMulticoreNrOfCoresSlave
+ 1
+
+
+ OCMulticoreAMPConfigType
+ 0
+
+
+ OCMulticoreSessionFile
+
+
+
+ OCTpiuBaseOption
+ 1
+
+
+
+
+ ARMSIM_ID
+ 2
+
+ 1
+ 1
+ 1
+
+ OCSimDriverInfo
+ 1
+
+
+ OCSimEnablePSP
+ 0
+
+
+ OCSimPspOverrideConfig
+ 0
+
+
+ OCSimPspConfigFile
+
+
+
+
+
+ CADI_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ CCadiMemory
+ 1
+
+
+ Fast Model
+
+
+
+ CCADILogFileCheck
+ 0
+
+
+ CCADILogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ CMSISDAP_ID
+ 2
+
+ 4
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ CMSISDAPResetList
+ 1
+ 10
+
+
+ CMSISDAPHWResetDuration
+ 300
+
+
+ CMSISDAPHWResetDelay
+ 200
+
+
+ CMSISDAPDoLogfile
+ 0
+
+
+ CMSISDAPLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CMSISDAPInterfaceRadio
+ 0
+
+
+ CMSISDAPInterfaceCmdLine
+ 0
+
+
+ CMSISDAPMultiTargetEnable
+ 0
+
+
+ CMSISDAPMultiTarget
+ 0
+
+
+ CMSISDAPJtagSpeedList
+ 0
+ 0
+
+
+ CMSISDAPBreakpointRadio
+ 0
+
+
+ CMSISDAPRestoreBreakpointsCheck
+ 0
+
+
+ CMSISDAPUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ CMSISDAPMultiCPUEnable
+ 0
+
+
+ CMSISDAPMultiCPUNumber
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+
+ CMSISDAPProbeConfigRadio
+ 0
+
+
+ CMSISDAPSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+
+ OCJetEmuParams
+ 1
+
+
+ CCCMSISDAPUsbSerialNo
+
+
+
+ CCCMSISDAPUsbSerialNoSelect
+ 0
+
+
+
+
+ GDBSERVER_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ TCPIP
+ aaa.bbb.ccc.ddd
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJTagBreakpointRadio
+ 0
+
+
+ CCJTagDoUpdateBreakpoints
+ 0
+
+
+ CCJTagUpdateBreakpoints
+ _call_main
+
+
+
+
+ IJET_ID
+ 2
+
+ 9
+ 1
+ 1
+
+ CatchSFERR
+ 1
+
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ IjetResetList
+ 1
+ 10
+
+
+ IjetHWResetDuration
+ 300
+
+
+ IjetHWResetDelay
+ 200
+
+
+ IjetPowerFromProbe
+ 1
+
+
+ IjetPowerRadio
+ 0
+
+
+ IjetDoLogfile
+ 0
+
+
+ IjetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ IjetInterfaceRadio
+ 0
+
+
+ IjetInterfaceCmdLine
+ 0
+
+
+ IjetMultiTargetEnable
+ 0
+
+
+ IjetMultiTarget
+ 0
+
+
+ IjetScanChainNonARMDevices
+ 0
+
+
+ IjetIRLength
+ 0
+
+
+ IjetJtagSpeedList
+ 0
+ 0
+
+
+ IjetProtocolRadio
+ 0
+
+
+ IjetSwoPin
+ 0
+
+
+ IjetCpuClockEdit
+ 72.0
+
+
+ IjetSwoPrescalerList
+ 1
+ 0
+
+
+ IjetBreakpointRadio
+ 0
+
+
+ IjetRestoreBreakpointsCheck
+ 0
+
+
+ IjetUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 0
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 0
+
+
+ RDICatchPrefetch
+ 0
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 0
+
+
+ CatchNOCPERR
+ 0
+
+
+ CatchCHKERR
+ 0
+
+
+ CatchSTATERR
+ 0
+
+
+ CatchBUSERR
+ 0
+
+
+ CatchINTERR
+ 0
+
+
+ CatchHARDERR
+ 0
+
+
+ CatchDummy
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+
+ IjetProbeConfigRadio
+ 0
+
+
+ IjetMultiCPUEnable
+ 0
+
+
+ IjetMultiCPUNumber
+ 0
+
+
+ IjetSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+
+ OCJetEmuParams
+ 1
+
+
+ IjetPreferETB
+ 1
+
+
+ IjetTraceSettingsList
+ 0
+ 0
+
+
+ IjetTraceSizeList
+ 0
+ 4
+
+
+ FlashBoardPathSlave
+ 0
+
+
+ CCIjetUsbSerialNo
+
+
+
+ CCIjetUsbSerialNoSelect
+ 0
+
+
+ CatchV8ARReset
+ 0
+
+
+ CatchV8AREREL1NS
+ 0
+
+
+ CatchV8AREREL1S
+ 0
+
+
+ CatchV8AREREL2NS
+ 0
+
+
+ CatchV8AREREL3S
+ 0
+
+
+ CatchV8AREEL1NS
+ 0
+
+
+ CatchV8ARREL1NS
+ 0
+
+
+ CatchV8AREEL1S
+ 0
+
+
+ CatchV8ARREL1S
+ 0
+
+
+ CatchV8AREEL2NS
+ 0
+
+
+ CatchV8ARREL2NS
+ 0
+
+
+ CatchV8AREEL3S
+ 0
+
+
+ CatchV8ARREL3S
+ 0
+
+
+
+
+ JLINK_ID
+ 2
+
+ 16
+ 1
+ 1
+
+ CCCatchSFERR
+ 0
+
+
+ JLinkSpeed
+ 32
+
+
+ CCJLinkDoLogfile
+ 0
+
+
+ CCJLinkLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJLinkHWResetDelay
+ 0
+
+
+ OCDriverInfo
+ 1
+
+
+ JLinkInitialSpeed
+ 32
+
+
+ CCDoJlinkMultiTarget
+ 0
+
+
+ CCScanChainNonARMDevices
+ 0
+
+
+ CCJLinkMultiTarget
+ 0
+
+
+ CCJLinkIRLength
+ 0
+
+
+ CCJLinkCommRadio
+ 0
+
+
+ CCJLinkTCPIP
+ aaa.bbb.ccc.ddd
+
+
+ CCJLinkSpeedRadioV2
+ 0
+
+
+ CCUSBDevice
+ 1
+ 1
+
+
+ CCRDICatchReset
+ 0
+
+
+ CCRDICatchUndef
+ 0
+
+
+ CCRDICatchSWI
+ 0
+
+
+ CCRDICatchData
+ 0
+
+
+ CCRDICatchPrefetch
+ 0
+
+
+ CCRDICatchIRQ
+ 0
+
+
+ CCRDICatchFIQ
+ 0
+
+
+ CCJLinkBreakpointRadio
+ 0
+
+
+ CCJLinkDoUpdateBreakpoints
+ 0
+
+
+ CCJLinkUpdateBreakpoints
+ _call_main
+
+
+ CCJLinkInterfaceRadio
+ 0
+
+
+ CCJLinkResetList
+ 6
+ 5
+
+
+ CCJLinkInterfaceCmdLine
+ 0
+
+
+ CCCatchCORERESET
+ 0
+
+
+ CCCatchMMERR
+ 0
+
+
+ CCCatchNOCPERR
+ 0
+
+
+ CCCatchCHRERR
+ 0
+
+
+ CCCatchSTATERR
+ 0
+
+
+ CCCatchBUSERR
+ 0
+
+
+ CCCatchINTERR
+ 0
+
+
+ CCCatchHARDERR
+ 0
+
+
+ CCCatchDummy
+ 0
+
+
+ OCJLinkScriptFile
+ 1
+
+
+ CCJLinkUsbSerialNo
+
+
+
+ CCTcpIpAlt
+ 0
+ 0
+
+
+ CCJLinkTcpIpSerialNo
+
+
+
+ CCCpuClockEdit
+ 72.0
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ OCJLinkTraceSource
+ 0
+
+
+ OCJLinkTraceSourceDummy
+ 0
+
+
+ OCJLinkDeviceName
+ 1
+
+
+
+
+ LMIFTDI_ID
+ 2
+
+ 3
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ LmiftdiSpeed
+ 500
+
+
+ CCLmiftdiDoLogfile
+ 0
+
+
+ CCLmiftdiLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCLmiFtdiInterfaceRadio
+ 0
+
+
+ CCLmiFtdiInterfaceCmdLine
+ 0
+
+
+ CCLmiftdiUsbSerialNo
+
+
+
+ CCLmiftdiUsbSerialNoSelect
+ 0
+
+
+ CCLmiftdiResetList
+ 0
+ 0
+
+
+
+
+ NULINK_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+
+
+ PEMICRO_ID
+ 2
+
+ 3
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCJPEMicroShowSettings
+ 0
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+
+
+ STLINK_ID
+ 2
+
+ 8
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCSTLinkInterfaceRadio
+ 0
+
+
+ CCSTLinkInterfaceCmdLine
+ 0
+
+
+ CCSTLinkResetList
+ 3
+ 0
+
+
+ CCCpuClockEdit
+ 72.0
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCSTLinkDoUpdateBreakpoints
+ 0
+
+
+ CCSTLinkUpdateBreakpoints
+ _call_main
+
+
+ CCSTLinkCatchCORERESET
+ 0
+
+
+ CCSTLinkCatchMMERR
+ 0
+
+
+ CCSTLinkCatchNOCPERR
+ 0
+
+
+ CCSTLinkCatchCHRERR
+ 0
+
+
+ CCSTLinkCatchSTATERR
+ 0
+
+
+ CCSTLinkCatchBUSERR
+ 0
+
+
+ CCSTLinkCatchINTERR
+ 0
+
+
+ CCSTLinkCatchSFERR
+ 0
+
+
+ CCSTLinkCatchHARDERR
+ 0
+
+
+ CCSTLinkCatchDummy
+ 0
+
+
+ CCSTLinkUsbSerialNo
+
+
+
+ CCSTLinkUsbSerialNoSelect
+ 0
+
+
+ CCSTLinkJtagSpeedList
+ 2
+ 0
+
+
+ CCSTLinkDAPNumber
+
+
+
+ CCSTLinkDebugAccessPortRadio
+ 0
+
+
+ CCSTLinkUseServerSelect
+ 0
+
+
+ CCSTLinkProbeList
+ 1
+ 0
+
+
+ CCSTLinkTargetVccEnable
+ 1
+
+
+ CCSTLinkTargetVoltage
+ ###Uninitialized###
+
+
+
+
+ THIRDPARTY_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ CThirdPartyDriverDll
+ ###Uninitialized###
+
+
+ CThirdPartyLogFileCheck
+ 0
+
+
+ CThirdPartyLogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ TIFET_ID
+ 2
+
+ 1
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCMSPFetResetList
+ 0
+ 0
+
+
+ CCMSPFetInterfaceRadio
+ 0
+
+
+ CCMSPFetInterfaceCmdLine
+ 0
+
+
+ CCMSPFetTargetVccTypeDefault
+ 0
+
+
+ CCMSPFetTargetVoltage
+ ###Uninitialized###
+
+
+ CCMSPFetVCCDefault
+ 1
+
+
+ CCMSPFetTargetSettlingtime
+ 0
+
+
+ CCMSPFetRadioJtagSpeedType
+ 1
+
+
+ CCMSPFetConnection
+ 0
+ 0
+
+
+ CCMSPFetUsbComPort
+ Automatic
+
+
+ CCMSPFetAllowAccessToBSL
+ 0
+
+
+ CCMSPFetDoLogfile
+ 0
+
+
+ CCMSPFetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCMSPFetRadioEraseFlash
+ 1
+
+
+
+
+ XDS100_ID
+ 2
+
+ 9
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ TIPackageOverride
+ 0
+
+
+ TIPackage
+
+
+
+ BoardFile
+
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCXds100BreakpointRadio
+ 0
+
+
+ CCXds100DoUpdateBreakpoints
+ 0
+
+
+ CCXds100UpdateBreakpoints
+ _call_main
+
+
+ CCXds100CatchReset
+ 0
+
+
+ CCXds100CatchUndef
+ 0
+
+
+ CCXds100CatchSWI
+ 0
+
+
+ CCXds100CatchData
+ 0
+
+
+ CCXds100CatchPrefetch
+ 0
+
+
+ CCXds100CatchIRQ
+ 0
+
+
+ CCXds100CatchFIQ
+ 0
+
+
+ CCXds100CatchCORERESET
+ 0
+
+
+ CCXds100CatchMMERR
+ 0
+
+
+ CCXds100CatchNOCPERR
+ 0
+
+
+ CCXds100CatchCHRERR
+ 0
+
+
+ CCXds100CatchSTATERR
+ 0
+
+
+ CCXds100CatchBUSERR
+ 0
+
+
+ CCXds100CatchINTERR
+ 0
+
+
+ CCXds100CatchSFERR
+ 0
+
+
+ CCXds100CatchHARDERR
+ 0
+
+
+ CCXds100CatchDummy
+ 0
+
+
+ CCXds100CpuClockEdit
+
+
+
+ CCXds100SwoClockAuto
+ 0
+
+
+ CCXds100SwoClockEdit
+ 1000
+
+
+ CCXds100HWResetDelay
+ 0
+
+
+ CCXds100ResetList
+ 1
+ 0
+
+
+ CCXds100UsbSerialNo
+
+
+
+ CCXds100UsbSerialNoSelect
+ 0
+
+
+ CCXds100JtagSpeedList
+ 0
+ 0
+
+
+ CCXds100InterfaceRadio
+ 0
+
+
+ CCXds100InterfaceCmdLine
+ 0
+
+
+ CCXds100ProbeList
+ 0
+ 0
+
+
+ CCXds100SWOPortRadio
+ 0
+
+
+ CCXds100SWOPort
+ 1
+
+
+ CCXDSTargetVccEnable
+ 0
+
+
+ CCXDSTargetVoltage
+ ###Uninitialized###
+
+
+ OCXDSDigitalStatesConfigFile
+ 1
+
+
+ OCSelectedCoreName
+ 1
+
+
+
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+ 0
+
+
+
+
diff --git a/lesson-01/simulator-iar/project.ewp b/lesson-01/simulator-iar/project.ewp
index 11aa663..6475c8c 100644
--- a/lesson-01/simulator-iar/project.ewp
+++ b/lesson-01/simulator-iar/project.ewp
@@ -74,7 +74,7 @@
OGChipSelectEditMenu
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
GenLowLevelInterface
@@ -120,7 +120,7 @@
GFPUDeviceSlave
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
FPU2
diff --git a/lesson-02/simulator-iar/project.ewd b/lesson-02/simulator-iar/project.ewd
index 0f172bb..e6a0eaf 100644
--- a/lesson-02/simulator-iar/project.ewd
+++ b/lesson-02/simulator-iar/project.ewd
@@ -44,7 +44,7 @@
MemFile
- $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\LM4F120H5QR.ddf
+ $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf
RunToEnable
@@ -92,7 +92,7 @@
UseFlashLoader
- 0
+ 1
CLowLevel
@@ -112,7 +112,7 @@
FlashLoadersV3
- $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashLM4FxxxHxx.board
+ $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashTC4_H6_o.board
OCImagesSuppressCheck1
diff --git a/lesson-02/simulator-iar/project.ewp b/lesson-02/simulator-iar/project.ewp
index 2e2674d..6475c8c 100644
--- a/lesson-02/simulator-iar/project.ewp
+++ b/lesson-02/simulator-iar/project.ewp
@@ -62,7 +62,7 @@
RTDescription
- Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
+ A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
OGProductVersion
@@ -74,7 +74,7 @@
OGChipSelectEditMenu
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
GenLowLevelInterface
@@ -120,7 +120,7 @@
GFPUDeviceSlave
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
FPU2
@@ -756,7 +756,7 @@
IlinkIcfFile
- $TOOLKIT_DIR$/config/linker/TexasInstruments/LM4F120H5QR.icf
+ $TOOLKIT_DIR$\CONFIG\generic.icf
IlinkIcfFileSlave
@@ -816,7 +816,7 @@
IlinkProgramEntryLabel
- __iar_program_start
+
DoFill
@@ -989,7 +989,7 @@
IlinkTrustzoneImportLibraryOut
- project_import_lib.o
+ ###Unitialized###
OILinkExtraOption
diff --git a/lesson-03/simulator-iar/lesson.ewd b/lesson-03/simulator-iar/lesson.ewd
deleted file mode 100644
index 8f4e52e..0000000
--- a/lesson-03/simulator-iar/lesson.ewd
+++ /dev/null
@@ -1,3104 +0,0 @@
-
-
- 3
-
- Debug
-
- ARM
-
- 1
-
- C-SPY
- 2
-
- 32
- 1
- 1
-
- CInput
- 1
-
-
- CEndian
- 1
-
-
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- 1
-
-
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-
-
- MacOverride
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-
-
- MacFile
-
-
-
- MemOverride
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-
-
- MemFile
- $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf
-
-
- RunToEnable
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-
-
- RunToName
- main
-
-
- CExtraOptionsCheck
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-
-
- CExtraOptions
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-
-
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-
-
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-
-
- OCDownloadSuppressDownload
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-
-
- OCDownloadVerifyAll
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-
-
- OCProductVersion
- 9.32.1.54977
-
-
- OCDynDriverList
- ARMSIM_ID
-
-
- OCLastSavedByProductVersion
- 9.32.1.54977
-
-
- UseFlashLoader
- 1
-
-
- CLowLevel
- 1
-
-
- OCBE8Slave
- 1
-
-
- MacFile2
-
-
-
- CDevice
- 1
-
-
- FlashLoadersV3
- $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashTC4_H6_o.board
-
-
- OCImagesSuppressCheck1
- 0
-
-
- OCImagesPath1
-
-
-
- OCImagesSuppressCheck2
- 0
-
-
- OCImagesPath2
-
-
-
- OCImagesSuppressCheck3
- 0
-
-
- OCImagesPath3
-
-
-
- OverrideDefFlashBoard
- 0
-
-
- OCImagesOffset1
-
-
-
- OCImagesOffset2
-
-
-
- OCImagesOffset3
-
-
-
- OCImagesUse1
- 0
-
-
- OCImagesUse2
- 0
-
-
- OCImagesUse3
- 0
-
-
- OCDeviceConfigMacroFile
- 1
-
-
- OCDebuggerExtraOption
- 1
-
-
- OCAllMTBOptions
- 1
-
-
- OCMulticoreNrOfCores
- 1
-
-
- OCMulticoreWorkspace
-
-
-
- OCMulticoreSlaveProject
-
-
-
- OCMulticoreSlaveConfiguration
-
-
-
- OCDownloadExtraImage
- 1
-
-
- OCAttachSlave
- 0
-
-
- MassEraseBeforeFlashing
- 0
-
-
- OCMulticoreNrOfCoresSlave
- 1
-
-
- OCMulticoreAMPConfigType
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-
-
- OCMulticoreSessionFile
-
-
-
- OCTpiuBaseOption
- 1
-
-
-
-
- ARMSIM_ID
- 2
-
- 1
- 1
- 1
-
- OCSimDriverInfo
- 1
-
-
- OCSimEnablePSP
- 0
-
-
- OCSimPspOverrideConfig
- 0
-
-
- OCSimPspConfigFile
-
-
-
-
-
- CADI_ID
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-
- 0
- 1
- 1
-
- CCadiMemory
- 1
-
-
- Fast Model
-
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-
- CCADILogFileCheck
- 0
-
-
- CCADILogFileEditB
- $PROJ_DIR$\cspycomm.log
-
-
- OCDriverInfo
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-
-
-
-
- CMSISDAP_ID
- 2
-
- 4
- 1
- 1
-
- OCDriverInfo
- 1
-
-
- OCIarProbeScriptFile
- 1
-
-
- CMSISDAPResetList
- 1
- 10
-
-
- CMSISDAPHWResetDuration
- 300
-
-
- CMSISDAPHWResetDelay
- 200
-
-
- CMSISDAPDoLogfile
- 0
-
-
- CMSISDAPLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CMSISDAPInterfaceRadio
- 1
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-
- CMSISDAPInterfaceCmdLine
- 0
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- CMSISDAPMultiTargetEnable
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-
-
- CMSISDAPMultiTarget
- 0
-
-
- CMSISDAPJtagSpeedList
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- 0
-
-
- CMSISDAPBreakpointRadio
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-
-
- CMSISDAPRestoreBreakpointsCheck
- 0
-
-
- CMSISDAPUpdateBreakpointsEdit
- _call_main
-
-
- RDICatchReset
- 0
-
-
- RDICatchUndef
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-
-
- RDICatchSWI
- 0
-
-
- RDICatchData
- 1
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-
- RDICatchPrefetch
- 1
-
-
- RDICatchIRQ
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-
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- CatchCORERESET
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- CatchMMERR
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-
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-
-
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-
-
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-
-
- CatchINTERR
- 1
-
-
- CatchSFERR
- 1
-
-
- CatchHARDERR
- 1
-
-
- CatchDummy
- 0
-
-
- CMSISDAPMultiCPUEnable
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-
-
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- 0
-
-
- OCProbeCfgOverride
- 0
-
-
- OCProbeConfig
-
-
-
- CMSISDAPProbeConfigRadio
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-
-
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-
-
- ICpuName
-
-
-
- OCJetEmuParams
- 1
-
-
- CCCMSISDAPUsbSerialNo
-
-
-
- CCCMSISDAPUsbSerialNoSelect
- 0
-
-
-
-
- GDBSERVER_ID
- 2
-
- 0
- 1
- 1
-
- OCDriverInfo
- 1
-
-
- TCPIP
- aaa.bbb.ccc.ddd
-
-
- DoLogfile
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-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCJTagBreakpointRadio
- 0
-
-
- CCJTagDoUpdateBreakpoints
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-
-
- CCJTagUpdateBreakpoints
- _call_main
-
-
-
-
- IJET_ID
- 2
-
- 9
- 1
- 1
-
- OCDriverInfo
- 1
-
-
- OCIarProbeScriptFile
- 1
-
-
- IjetResetList
- 1
- 10
-
-
- IjetHWResetDuration
- 300
-
-
- IjetHWResetDelay
- 200
-
-
- IjetPowerFromProbe
- 1
-
-
- IjetPowerRadio
- 0
-
-
- IjetDoLogfile
- 0
-
-
- IjetLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- IjetInterfaceRadio
- 1
-
-
- IjetInterfaceCmdLine
- 0
-
-
- IjetMultiTargetEnable
- 0
-
-
- IjetMultiTarget
- 0
-
-
- IjetScanChainNonARMDevices
- 0
-
-
- IjetIRLength
- 0
-
-
- IjetJtagSpeedList
- 0
- 0
-
-
- IjetProtocolRadio
- 0
-
-
- IjetSwoPin
- 0
-
-
- IjetCpuClockEdit
-
-
-
- IjetSwoPrescalerList
- 1
- 0
-
-
- IjetBreakpointRadio
- 0
-
-
- IjetRestoreBreakpointsCheck
- 0
-
-
- IjetUpdateBreakpointsEdit
- _call_main
-
-
- RDICatchReset
- 0
-
-
- RDICatchUndef
- 1
-
-
- RDICatchSWI
- 0
-
-
- RDICatchData
- 1
-
-
- RDICatchPrefetch
- 1
-
-
- RDICatchIRQ
- 0
-
-
- RDICatchFIQ
- 0
-
-
- CatchCORERESET
- 0
-
-
- CatchMMERR
- 1
-
-
- CatchNOCPERR
- 1
-
-
- CatchCHKERR
- 1
-
-
- CatchSTATERR
- 1
-
-
- CatchBUSERR
- 1
-
-
- CatchINTERR
- 1
-
-
- CatchSFERR
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-
-
- CatchHARDERR
- 1
-
-
- CatchDummy
- 0
-
-
- OCProbeCfgOverride
- 0
-
-
- OCProbeConfig
-
-
-
- IjetProbeConfigRadio
- 0
-
-
- IjetMultiCPUEnable
- 0
-
-
- IjetMultiCPUNumber
- 0
-
-
- IjetSelectedCPUBehaviour
- 0
-
-
- ICpuName
-
-
-
- OCJetEmuParams
- 1
-
-
- IjetPreferETB
- 1
-
-
- IjetTraceSettingsList
- 0
- 0
-
-
- IjetTraceSizeList
- 0
- 4
-
-
- FlashBoardPathSlave
- 0
-
-
- CCIjetUsbSerialNo
-
-
-
- CCIjetUsbSerialNoSelect
- 0
-
-
- CatchV8ARReset
- 0
-
-
- CatchV8AREREL1NS
- 0
-
-
- CatchV8AREREL1S
- 0
-
-
- CatchV8AREREL2NS
- 0
-
-
- CatchV8AREREL3S
- 0
-
-
- CatchV8AREEL1NS
- 0
-
-
- CatchV8ARREL1NS
- 0
-
-
- CatchV8AREEL1S
- 0
-
-
- CatchV8ARREL1S
- 0
-
-
- CatchV8AREEL2NS
- 0
-
-
- CatchV8ARREL2NS
- 0
-
-
- CatchV8AREEL3S
- 0
-
-
- CatchV8ARREL3S
- 0
-
-
-
-
- JLINK_ID
- 2
-
- 16
- 1
- 1
-
- JLinkSpeed
- 1000
-
-
- CCJLinkDoLogfile
- 0
-
-
- CCJLinkLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCJLinkHWResetDelay
- 0
-
-
- OCDriverInfo
- 1
-
-
- JLinkInitialSpeed
- 1000
-
-
- CCDoJlinkMultiTarget
- 0
-
-
- CCScanChainNonARMDevices
- 0
-
-
- CCJLinkMultiTarget
- 0
-
-
- CCJLinkIRLength
- 0
-
-
- CCJLinkCommRadio
- 0
-
-
- CCJLinkTCPIP
- aaa.bbb.ccc.ddd
-
-
- CCJLinkSpeedRadioV2
- 0
-
-
- CCUSBDevice
- 1
- 1
-
-
- CCRDICatchReset
- 0
-
-
- CCRDICatchUndef
- 0
-
-
- CCRDICatchSWI
- 0
-
-
- CCRDICatchData
- 0
-
-
- CCRDICatchPrefetch
- 0
-
-
- CCRDICatchIRQ
- 0
-
-
- CCRDICatchFIQ
- 0
-
-
- CCJLinkBreakpointRadio
- 0
-
-
- CCJLinkDoUpdateBreakpoints
- 0
-
-
- CCJLinkUpdateBreakpoints
- _call_main
-
-
- CCJLinkInterfaceRadio
- 1
-
-
- CCJLinkResetList
- 6
- 5
-
-
- CCJLinkInterfaceCmdLine
- 0
-
-
- CCCatchCORERESET
- 0
-
-
- CCCatchMMERR
- 0
-
-
- CCCatchNOCPERR
- 0
-
-
- CCCatchCHRERR
- 0
-
-
- CCCatchSTATERR
- 0
-
-
- CCCatchBUSERR
- 0
-
-
- CCCatchINTERR
- 0
-
-
- CCCatchSFERR
- 0
-
-
- CCCatchHARDERR
- 0
-
-
- CCCatchDummy
- 0
-
-
- OCJLinkScriptFile
- 1
-
-
- CCJLinkUsbSerialNo
-
-
-
- CCTcpIpAlt
- 0
- 0
-
-
- CCJLinkTcpIpSerialNo
-
-
-
- CCCpuClockEdit
-
-
-
- CCSwoClockAuto
- 0
-
-
- CCSwoClockEdit
- 2000
-
-
- OCJLinkTraceSource
- 0
-
-
- OCJLinkTraceSourceDummy
- 0
-
-
- OCJLinkDeviceName
- 1
-
-
-
-
- LMIFTDI_ID
- 2
-
- 3
- 1
- 1
-
- OCDriverInfo
- 1
-
-
- LmiftdiSpeed
- 500
-
-
- CCLmiftdiDoLogfile
- 0
-
-
- CCLmiftdiLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCLmiFtdiInterfaceRadio
- 1
-
-
- CCLmiFtdiInterfaceCmdLine
- 0
-
-
- CCLmiftdiUsbSerialNo
-
-
-
- CCLmiftdiUsbSerialNoSelect
- 0
-
-
- CCLmiftdiResetList
- 0
- 0
-
-
-
-
- NULINK_ID
- 2
-
- 0
- 1
- 1
-
- OCDriverInfo
- 1
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
-
-
- PEMICRO_ID
- 2
-
- 3
- 1
- 1
-
- OCDriverInfo
- 1
-
-
- CCJPEMicroShowSettings
- 0
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
-
-
- STLINK_ID
- 2
-
- 8
- 1
- 1
-
- OCDriverInfo
- 1
-
-
- CCSTLinkInterfaceRadio
- 1
-
-
- CCSTLinkInterfaceCmdLine
- 0
-
-
- CCSTLinkResetList
- 3
- 0
-
-
- CCCpuClockEdit
-
-
-
- CCSwoClockAuto
- 1
-
-
- CCSwoClockEdit
- 2000
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCSTLinkDoUpdateBreakpoints
- 0
-
-
- CCSTLinkUpdateBreakpoints
- _call_main
-
-
- CCSTLinkCatchCORERESET
- 0
-
-
- CCSTLinkCatchMMERR
- 0
-
-
- CCSTLinkCatchNOCPERR
- 0
-
-
- CCSTLinkCatchCHRERR
- 0
-
-
- CCSTLinkCatchSTATERR
- 0
-
-
- CCSTLinkCatchBUSERR
- 0
-
-
- CCSTLinkCatchINTERR
- 0
-
-
- CCSTLinkCatchSFERR
- 0
-
-
- CCSTLinkCatchHARDERR
- 0
-
-
- CCSTLinkCatchDummy
- 0
-
-
- CCSTLinkUsbSerialNo
-
-
-
- CCSTLinkUsbSerialNoSelect
- 0
-
-
- CCSTLinkJtagSpeedList
- 2
- 0
-
-
- CCSTLinkDAPNumber
-
-
-
- CCSTLinkDebugAccessPortRadio
- 0
-
-
- CCSTLinkUseServerSelect
- 0
-
-
- CCSTLinkProbeList
- 1
- 0
-
-
- CCSTLinkTargetVccEnable
- 1
-
-
- CCSTLinkTargetVoltage
- ###Uninitialized###
-
-
-
-
- THIRDPARTY_ID
- 2
-
- 0
- 1
- 1
-
- CThirdPartyDriverDll
- ###Uninitialized###
-
-
- CThirdPartyLogFileCheck
- 0
-
-
- CThirdPartyLogFileEditB
- $PROJ_DIR$\cspycomm.log
-
-
- OCDriverInfo
- 1
-
-
-
-
- TIFET_ID
- 2
-
- 1
- 1
- 1
-
- OCDriverInfo
- 1
-
-
- CCMSPFetResetList
- 0
- 0
-
-
- CCMSPFetInterfaceRadio
- 0
-
-
- CCMSPFetInterfaceCmdLine
- 0
-
-
- CCMSPFetTargetVccTypeDefault
- 0
-
-
- CCMSPFetTargetVoltage
- ###Uninitialized###
-
-
- CCMSPFetVCCDefault
- 1
-
-
- CCMSPFetTargetSettlingtime
- 0
-
-
- CCMSPFetRadioJtagSpeedType
- 1
-
-
- CCMSPFetConnection
- 0
- 0
-
-
- CCMSPFetUsbComPort
- Automatic
-
-
- CCMSPFetAllowAccessToBSL
- 0
-
-
- CCMSPFetDoLogfile
- 0
-
-
- CCMSPFetLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCMSPFetRadioEraseFlash
- 1
-
-
-
-
- XDS100_ID
- 2
-
- 9
- 1
- 1
-
- OCDriverInfo
- 1
-
-
- TIPackageOverride
- 0
-
-
- TIPackage
-
-
-
- BoardFile
-
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCXds100BreakpointRadio
- 0
-
-
- CCXds100DoUpdateBreakpoints
- 0
-
-
- CCXds100UpdateBreakpoints
- _call_main
-
-
- CCXds100CatchReset
- 0
-
-
- CCXds100CatchUndef
- 0
-
-
- CCXds100CatchSWI
- 0
-
-
- CCXds100CatchData
- 0
-
-
- CCXds100CatchPrefetch
- 0
-
-
- CCXds100CatchIRQ
- 0
-
-
- CCXds100CatchFIQ
- 0
-
-
- CCXds100CatchCORERESET
- 0
-
-
- CCXds100CatchMMERR
- 0
-
-
- CCXds100CatchNOCPERR
- 0
-
-
- CCXds100CatchCHRERR
- 0
-
-
- CCXds100CatchSTATERR
- 0
-
-
- CCXds100CatchBUSERR
- 0
-
-
- CCXds100CatchINTERR
- 0
-
-
- CCXds100CatchSFERR
- 0
-
-
- CCXds100CatchHARDERR
- 0
-
-
- CCXds100CatchDummy
- 0
-
-
- CCXds100CpuClockEdit
-
-
-
- CCXds100SwoClockAuto
- 0
-
-
- CCXds100SwoClockEdit
- 1000
-
-
- CCXds100HWResetDelay
- 0
-
-
- CCXds100ResetList
- 1
- 0
-
-
- CCXds100UsbSerialNo
-
-
-
- CCXds100UsbSerialNoSelect
- 0
-
-
- CCXds100JtagSpeedList
- 0
- 0
-
-
- CCXds100InterfaceRadio
- 2
-
-
- CCXds100InterfaceCmdLine
- 0
-
-
- CCXds100ProbeList
- 0
- 3
-
-
- CCXds100SWOPortRadio
- 0
-
-
- CCXds100SWOPort
- 1
-
-
- CCXDSTargetVccEnable
- 0
-
-
- CCXDSTargetVoltage
- ###Uninitialized###
-
-
- OCXDSDigitalStatesConfigFile
- 1
-
-
- OCSelectedCoreName
- 1
-
-
-
-
-
- $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
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-
- $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
- 0
-
-
- $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
- 0
-
-
- $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
- 0
-
-
- $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
- 0
-
-
-
-
- Release
-
- ARM
-
- 0
-
- C-SPY
- 2
-
- 32
- 1
- 0
-
- CInput
- 1
-
-
- CEndian
- 1
-
-
- CProcessor
- 1
-
-
- OCVariant
- 0
-
-
- MacOverride
- 0
-
-
- MacFile
-
-
-
- MemOverride
- 0
-
-
- MemFile
-
-
-
- RunToEnable
- 1
-
-
- RunToName
- main
-
-
- CExtraOptionsCheck
- 0
-
-
- CExtraOptions
-
-
-
- CFpuProcessor
- 1
-
-
- OCDDFArgumentProducer
-
-
-
- OCDownloadSuppressDownload
- 0
-
-
- OCDownloadVerifyAll
- 0
-
-
- OCProductVersion
- 9.32.1.54977
-
-
- OCDynDriverList
- ARMSIM_ID
-
-
- OCLastSavedByProductVersion
-
-
-
- UseFlashLoader
- 1
-
-
- CLowLevel
- 1
-
-
- OCBE8Slave
- 1
-
-
- MacFile2
-
-
-
- CDevice
- 1
-
-
- FlashLoadersV3
-
-
-
- OCImagesSuppressCheck1
- 0
-
-
- OCImagesPath1
-
-
-
- OCImagesSuppressCheck2
- 0
-
-
- OCImagesPath2
-
-
-
- OCImagesSuppressCheck3
- 0
-
-
- OCImagesPath3
-
-
-
- OverrideDefFlashBoard
- 0
-
-
- OCImagesOffset1
-
-
-
- OCImagesOffset2
-
-
-
- OCImagesOffset3
-
-
-
- OCImagesUse1
- 0
-
-
- OCImagesUse2
- 0
-
-
- OCImagesUse3
- 0
-
-
- OCDeviceConfigMacroFile
- 1
-
-
- OCDebuggerExtraOption
- 1
-
-
- OCAllMTBOptions
- 1
-
-
- OCMulticoreNrOfCores
-
-
-
- OCMulticoreWorkspace
-
-
-
- OCMulticoreSlaveProject
-
-
-
- OCMulticoreSlaveConfiguration
-
-
-
- OCDownloadExtraImage
- 1
-
-
- OCAttachSlave
- 0
-
-
- MassEraseBeforeFlashing
- 0
-
-
- OCMulticoreNrOfCoresSlave
- 1
-
-
- OCMulticoreAMPConfigType
- 0
-
-
- OCMulticoreSessionFile
-
-
-
- OCTpiuBaseOption
- 1
-
-
-
-
- ARMSIM_ID
- 2
-
- 1
- 1
- 0
-
- OCSimDriverInfo
- 1
-
-
- OCSimEnablePSP
- 0
-
-
- OCSimPspOverrideConfig
- 0
-
-
- OCSimPspConfigFile
-
-
-
-
-
- CADI_ID
- 2
-
- 0
- 1
- 0
-
- CCadiMemory
- 1
-
-
- Fast Model
-
-
-
- CCADILogFileCheck
- 0
-
-
- CCADILogFileEditB
- $PROJ_DIR$\cspycomm.log
-
-
- OCDriverInfo
- 1
-
-
-
-
- CMSISDAP_ID
- 2
-
- 4
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- OCIarProbeScriptFile
- 1
-
-
- CMSISDAPResetList
- 1
- 10
-
-
- CMSISDAPHWResetDuration
- 300
-
-
- CMSISDAPHWResetDelay
- 200
-
-
- CMSISDAPDoLogfile
- 0
-
-
- CMSISDAPLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CMSISDAPInterfaceRadio
- 1
-
-
- CMSISDAPInterfaceCmdLine
- 0
-
-
- CMSISDAPMultiTargetEnable
- 0
-
-
- CMSISDAPMultiTarget
- 0
-
-
- CMSISDAPJtagSpeedList
- 0
- 0
-
-
- CMSISDAPBreakpointRadio
- 0
-
-
- CMSISDAPRestoreBreakpointsCheck
- 0
-
-
- CMSISDAPUpdateBreakpointsEdit
- _call_main
-
-
- RDICatchReset
- 0
-
-
- RDICatchUndef
- 1
-
-
- RDICatchSWI
- 0
-
-
- RDICatchData
- 1
-
-
- RDICatchPrefetch
- 1
-
-
- RDICatchIRQ
- 0
-
-
- RDICatchFIQ
- 0
-
-
- CatchCORERESET
- 0
-
-
- CatchMMERR
- 1
-
-
- CatchNOCPERR
- 1
-
-
- CatchCHKERR
- 1
-
-
- CatchSTATERR
- 1
-
-
- CatchBUSERR
- 1
-
-
- CatchINTERR
- 1
-
-
- CatchSFERR
- 1
-
-
- CatchHARDERR
- 1
-
-
- CatchDummy
- 0
-
-
- CMSISDAPMultiCPUEnable
- 0
-
-
- CMSISDAPMultiCPUNumber
- 0
-
-
- OCProbeCfgOverride
- 0
-
-
- OCProbeConfig
-
-
-
- CMSISDAPProbeConfigRadio
- 0
-
-
- CMSISDAPSelectedCPUBehaviour
- 0
-
-
- ICpuName
-
-
-
- OCJetEmuParams
- 1
-
-
- CCCMSISDAPUsbSerialNo
-
-
-
- CCCMSISDAPUsbSerialNoSelect
- 0
-
-
-
-
- GDBSERVER_ID
- 2
-
- 0
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- TCPIP
- aaa.bbb.ccc.ddd
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCJTagBreakpointRadio
- 0
-
-
- CCJTagDoUpdateBreakpoints
- 0
-
-
- CCJTagUpdateBreakpoints
- _call_main
-
-
-
-
- IJET_ID
- 2
-
- 9
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- OCIarProbeScriptFile
- 1
-
-
- IjetResetList
- 1
- 10
-
-
- IjetHWResetDuration
- 300
-
-
- IjetHWResetDelay
- 200
-
-
- IjetPowerFromProbe
- 1
-
-
- IjetPowerRadio
- 0
-
-
- IjetDoLogfile
- 0
-
-
- IjetLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- IjetInterfaceRadio
- 1
-
-
- IjetInterfaceCmdLine
- 0
-
-
- IjetMultiTargetEnable
- 0
-
-
- IjetMultiTarget
- 0
-
-
- IjetScanChainNonARMDevices
- 0
-
-
- IjetIRLength
- 0
-
-
- IjetJtagSpeedList
- 0
- 0
-
-
- IjetProtocolRadio
- 0
-
-
- IjetSwoPin
- 0
-
-
- IjetCpuClockEdit
-
-
-
- IjetSwoPrescalerList
- 1
- 0
-
-
- IjetBreakpointRadio
- 0
-
-
- IjetRestoreBreakpointsCheck
- 0
-
-
- IjetUpdateBreakpointsEdit
- _call_main
-
-
- RDICatchReset
- 0
-
-
- RDICatchUndef
- 1
-
-
- RDICatchSWI
- 0
-
-
- RDICatchData
- 1
-
-
- RDICatchPrefetch
- 1
-
-
- RDICatchIRQ
- 0
-
-
- RDICatchFIQ
- 0
-
-
- CatchCORERESET
- 0
-
-
- CatchMMERR
- 1
-
-
- CatchNOCPERR
- 1
-
-
- CatchCHKERR
- 1
-
-
- CatchSTATERR
- 1
-
-
- CatchBUSERR
- 1
-
-
- CatchINTERR
- 1
-
-
- CatchSFERR
- 1
-
-
- CatchHARDERR
- 1
-
-
- CatchDummy
- 0
-
-
- OCProbeCfgOverride
- 0
-
-
- OCProbeConfig
-
-
-
- IjetProbeConfigRadio
- 0
-
-
- IjetMultiCPUEnable
- 0
-
-
- IjetMultiCPUNumber
- 0
-
-
- IjetSelectedCPUBehaviour
- 0
-
-
- ICpuName
-
-
-
- OCJetEmuParams
- 1
-
-
- IjetPreferETB
- 1
-
-
- IjetTraceSettingsList
- 0
- 0
-
-
- IjetTraceSizeList
- 0
- 4
-
-
- FlashBoardPathSlave
- 0
-
-
- CCIjetUsbSerialNo
-
-
-
- CCIjetUsbSerialNoSelect
- 0
-
-
- CatchV8ARReset
- 0
-
-
- CatchV8AREREL1NS
- 0
-
-
- CatchV8AREREL1S
- 0
-
-
- CatchV8AREREL2NS
- 0
-
-
- CatchV8AREREL3S
- 0
-
-
- CatchV8AREEL1NS
- 0
-
-
- CatchV8ARREL1NS
- 0
-
-
- CatchV8AREEL1S
- 0
-
-
- CatchV8ARREL1S
- 0
-
-
- CatchV8AREEL2NS
- 0
-
-
- CatchV8ARREL2NS
- 0
-
-
- CatchV8AREEL3S
- 0
-
-
- CatchV8ARREL3S
- 0
-
-
-
-
- JLINK_ID
- 2
-
- 16
- 1
- 0
-
- JLinkSpeed
- 1000
-
-
- CCJLinkDoLogfile
- 0
-
-
- CCJLinkLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCJLinkHWResetDelay
- 0
-
-
- OCDriverInfo
- 1
-
-
- JLinkInitialSpeed
- 1000
-
-
- CCDoJlinkMultiTarget
- 0
-
-
- CCScanChainNonARMDevices
- 0
-
-
- CCJLinkMultiTarget
- 0
-
-
- CCJLinkIRLength
- 0
-
-
- CCJLinkCommRadio
- 0
-
-
- CCJLinkTCPIP
- aaa.bbb.ccc.ddd
-
-
- CCJLinkSpeedRadioV2
- 0
-
-
- CCUSBDevice
- 1
- 1
-
-
- CCRDICatchReset
- 0
-
-
- CCRDICatchUndef
- 0
-
-
- CCRDICatchSWI
- 0
-
-
- CCRDICatchData
- 0
-
-
- CCRDICatchPrefetch
- 0
-
-
- CCRDICatchIRQ
- 0
-
-
- CCRDICatchFIQ
- 0
-
-
- CCJLinkBreakpointRadio
- 0
-
-
- CCJLinkDoUpdateBreakpoints
- 0
-
-
- CCJLinkUpdateBreakpoints
- _call_main
-
-
- CCJLinkInterfaceRadio
- 1
-
-
- CCJLinkResetList
- 6
- 5
-
-
- CCJLinkInterfaceCmdLine
- 0
-
-
- CCCatchCORERESET
- 0
-
-
- CCCatchMMERR
- 0
-
-
- CCCatchNOCPERR
- 0
-
-
- CCCatchCHRERR
- 0
-
-
- CCCatchSTATERR
- 0
-
-
- CCCatchBUSERR
- 0
-
-
- CCCatchINTERR
- 0
-
-
- CCCatchSFERR
- 0
-
-
- CCCatchHARDERR
- 0
-
-
- CCCatchDummy
- 0
-
-
- OCJLinkScriptFile
- 1
-
-
- CCJLinkUsbSerialNo
-
-
-
- CCTcpIpAlt
- 0
- 0
-
-
- CCJLinkTcpIpSerialNo
-
-
-
- CCCpuClockEdit
-
-
-
- CCSwoClockAuto
- 0
-
-
- CCSwoClockEdit
- 2000
-
-
- OCJLinkTraceSource
- 0
-
-
- OCJLinkTraceSourceDummy
- 0
-
-
- OCJLinkDeviceName
- 1
-
-
-
-
- LMIFTDI_ID
- 2
-
- 3
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- LmiftdiSpeed
- 500
-
-
- CCLmiftdiDoLogfile
- 0
-
-
- CCLmiftdiLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCLmiFtdiInterfaceRadio
- 1
-
-
- CCLmiFtdiInterfaceCmdLine
- 0
-
-
- CCLmiftdiUsbSerialNo
-
-
-
- CCLmiftdiUsbSerialNoSelect
- 0
-
-
- CCLmiftdiResetList
- 0
- 0
-
-
-
-
- NULINK_ID
- 2
-
- 0
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
-
-
- PEMICRO_ID
- 2
-
- 3
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- CCJPEMicroShowSettings
- 0
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
-
-
- STLINK_ID
- 2
-
- 8
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- CCSTLinkInterfaceRadio
- 1
-
-
- CCSTLinkInterfaceCmdLine
- 0
-
-
- CCSTLinkResetList
- 3
- 0
-
-
- CCCpuClockEdit
-
-
-
- CCSwoClockAuto
- 1
-
-
- CCSwoClockEdit
- 2000
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCSTLinkDoUpdateBreakpoints
- 0
-
-
- CCSTLinkUpdateBreakpoints
- _call_main
-
-
- CCSTLinkCatchCORERESET
- 0
-
-
- CCSTLinkCatchMMERR
- 0
-
-
- CCSTLinkCatchNOCPERR
- 0
-
-
- CCSTLinkCatchCHRERR
- 0
-
-
- CCSTLinkCatchSTATERR
- 0
-
-
- CCSTLinkCatchBUSERR
- 0
-
-
- CCSTLinkCatchINTERR
- 0
-
-
- CCSTLinkCatchSFERR
- 0
-
-
- CCSTLinkCatchHARDERR
- 0
-
-
- CCSTLinkCatchDummy
- 0
-
-
- CCSTLinkUsbSerialNo
-
-
-
- CCSTLinkUsbSerialNoSelect
- 0
-
-
- CCSTLinkJtagSpeedList
- 2
- 0
-
-
- CCSTLinkDAPNumber
-
-
-
- CCSTLinkDebugAccessPortRadio
- 0
-
-
- CCSTLinkUseServerSelect
- 0
-
-
- CCSTLinkProbeList
- 1
- 0
-
-
- CCSTLinkTargetVccEnable
- 1
-
-
- CCSTLinkTargetVoltage
- ###Uninitialized###
-
-
-
-
- THIRDPARTY_ID
- 2
-
- 0
- 1
- 0
-
- CThirdPartyDriverDll
- ###Uninitialized###
-
-
- CThirdPartyLogFileCheck
- 0
-
-
- CThirdPartyLogFileEditB
- $PROJ_DIR$\cspycomm.log
-
-
- OCDriverInfo
- 1
-
-
-
-
- TIFET_ID
- 2
-
- 1
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- CCMSPFetResetList
- 0
- 0
-
-
- CCMSPFetInterfaceRadio
- 0
-
-
- CCMSPFetInterfaceCmdLine
- 0
-
-
- CCMSPFetTargetVccTypeDefault
- 0
-
-
- CCMSPFetTargetVoltage
- ###Uninitialized###
-
-
- CCMSPFetVCCDefault
- 1
-
-
- CCMSPFetTargetSettlingtime
- 0
-
-
- CCMSPFetRadioJtagSpeedType
- 1
-
-
- CCMSPFetConnection
- 0
- 0
-
-
- CCMSPFetUsbComPort
- Automatic
-
-
- CCMSPFetAllowAccessToBSL
- 0
-
-
- CCMSPFetDoLogfile
- 0
-
-
- CCMSPFetLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCMSPFetRadioEraseFlash
- 1
-
-
-
-
- XDS100_ID
- 2
-
- 9
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- TIPackageOverride
- 0
-
-
- TIPackage
-
-
-
- BoardFile
-
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCXds100BreakpointRadio
- 0
-
-
- CCXds100DoUpdateBreakpoints
- 0
-
-
- CCXds100UpdateBreakpoints
- _call_main
-
-
- CCXds100CatchReset
- 0
-
-
- CCXds100CatchUndef
- 0
-
-
- CCXds100CatchSWI
- 0
-
-
- CCXds100CatchData
- 0
-
-
- CCXds100CatchPrefetch
- 0
-
-
- CCXds100CatchIRQ
- 0
-
-
- CCXds100CatchFIQ
- 0
-
-
- CCXds100CatchCORERESET
- 0
-
-
- CCXds100CatchMMERR
- 0
-
-
- CCXds100CatchNOCPERR
- 0
-
-
- CCXds100CatchCHRERR
- 0
-
-
- CCXds100CatchSTATERR
- 0
-
-
- CCXds100CatchBUSERR
- 0
-
-
- CCXds100CatchINTERR
- 0
-
-
- CCXds100CatchSFERR
- 0
-
-
- CCXds100CatchHARDERR
- 0
-
-
- CCXds100CatchDummy
- 0
-
-
- CCXds100CpuClockEdit
-
-
-
- CCXds100SwoClockAuto
- 0
-
-
- CCXds100SwoClockEdit
- 1000
-
-
- CCXds100HWResetDelay
- 0
-
-
- CCXds100ResetList
- 1
- 0
-
-
- CCXds100UsbSerialNo
-
-
-
- CCXds100UsbSerialNoSelect
- 0
-
-
- CCXds100JtagSpeedList
- 0
- 0
-
-
- CCXds100InterfaceRadio
- 2
-
-
- CCXds100InterfaceCmdLine
- 0
-
-
- CCXds100ProbeList
- 0
- 3
-
-
- CCXds100SWOPortRadio
- 0
-
-
- CCXds100SWOPort
- 1
-
-
- CCXDSTargetVccEnable
- 0
-
-
- CCXDSTargetVoltage
- ###Uninitialized###
-
-
- OCXDSDigitalStatesConfigFile
- 1
-
-
- OCSelectedCoreName
- 1
-
-
-
-
-
- $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
- 0
-
-
- $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
- 0
-
-
- $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
- 0
-
-
- $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
- 0
-
-
-
-
diff --git a/lesson-03/simulator-iar/lesson.eww b/lesson-03/simulator-iar/lesson.eww
deleted file mode 100644
index 89a5c55..0000000
--- a/lesson-03/simulator-iar/lesson.eww
+++ /dev/null
@@ -1,7 +0,0 @@
-
-
-
- $WS_DIR$\lesson.ewp
-
-
-
diff --git a/lesson-03/simulator-iar/project.ewd b/lesson-03/simulator-iar/project.ewd
new file mode 100644
index 0000000..e6a0eaf
--- /dev/null
+++ b/lesson-03/simulator-iar/project.ewd
@@ -0,0 +1,1554 @@
+
+
+ 3
+
+ Debug
+
+ ARM
+
+ 1
+
+ C-SPY
+ 2
+
+ 32
+ 1
+ 1
+
+ CInput
+ 1
+
+
+ CEndian
+ 1
+
+
+ CProcessor
+ 1
+
+
+ OCVariant
+ 0
+
+
+ MacOverride
+ 0
+
+
+ MacFile
+
+
+
+ MemOverride
+ 0
+
+
+ MemFile
+ $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf
+
+
+ RunToEnable
+ 1
+
+
+ RunToName
+ main
+
+
+ CExtraOptionsCheck
+ 0
+
+
+ CExtraOptions
+
+
+
+ CFpuProcessor
+ 1
+
+
+ OCDDFArgumentProducer
+
+
+
+ OCDownloadSuppressDownload
+ 0
+
+
+ OCDownloadVerifyAll
+ 1
+
+
+ OCProductVersion
+ 6.50.2.4581
+
+
+ OCDynDriverList
+ ARMSIM_ID
+
+
+ OCLastSavedByProductVersion
+ 9.32.1.54977
+
+
+ UseFlashLoader
+ 1
+
+
+ CLowLevel
+ 1
+
+
+ OCBE8Slave
+ 1
+
+
+ MacFile2
+
+
+
+ CDevice
+ 1
+
+
+ FlashLoadersV3
+ $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashTC4_H6_o.board
+
+
+ OCImagesSuppressCheck1
+ 0
+
+
+ OCImagesPath1
+
+
+
+ OCImagesSuppressCheck2
+ 0
+
+
+ OCImagesPath2
+
+
+
+ OCImagesSuppressCheck3
+ 0
+
+
+ OCImagesPath3
+
+
+
+ OverrideDefFlashBoard
+ 0
+
+
+ OCImagesOffset1
+
+
+
+ OCImagesOffset2
+
+
+
+ OCImagesOffset3
+
+
+
+ OCImagesUse1
+ 0
+
+
+ OCImagesUse2
+ 0
+
+
+ OCImagesUse3
+ 0
+
+
+ OCDeviceConfigMacroFile
+ 1
+
+
+ OCDebuggerExtraOption
+ 1
+
+
+ OCAllMTBOptions
+ 1
+
+
+ OCMulticoreNrOfCores
+ 1
+
+
+ OCMulticoreWorkspace
+
+
+
+ OCMulticoreSlaveProject
+
+
+
+ OCMulticoreSlaveConfiguration
+
+
+
+ OCDownloadExtraImage
+ 1
+
+
+ OCAttachSlave
+ 0
+
+
+ MassEraseBeforeFlashing
+ 0
+
+
+ OCMulticoreNrOfCoresSlave
+ 1
+
+
+ OCMulticoreAMPConfigType
+ 0
+
+
+ OCMulticoreSessionFile
+
+
+
+ OCTpiuBaseOption
+ 1
+
+
+
+
+ ARMSIM_ID
+ 2
+
+ 1
+ 1
+ 1
+
+ OCSimDriverInfo
+ 1
+
+
+ OCSimEnablePSP
+ 0
+
+
+ OCSimPspOverrideConfig
+ 0
+
+
+ OCSimPspConfigFile
+
+
+
+
+
+ CADI_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ CCadiMemory
+ 1
+
+
+ Fast Model
+
+
+
+ CCADILogFileCheck
+ 0
+
+
+ CCADILogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ CMSISDAP_ID
+ 2
+
+ 4
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ CMSISDAPResetList
+ 1
+ 10
+
+
+ CMSISDAPHWResetDuration
+ 300
+
+
+ CMSISDAPHWResetDelay
+ 200
+
+
+ CMSISDAPDoLogfile
+ 0
+
+
+ CMSISDAPLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CMSISDAPInterfaceRadio
+ 0
+
+
+ CMSISDAPInterfaceCmdLine
+ 0
+
+
+ CMSISDAPMultiTargetEnable
+ 0
+
+
+ CMSISDAPMultiTarget
+ 0
+
+
+ CMSISDAPJtagSpeedList
+ 0
+ 0
+
+
+ CMSISDAPBreakpointRadio
+ 0
+
+
+ CMSISDAPRestoreBreakpointsCheck
+ 0
+
+
+ CMSISDAPUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 1
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 1
+
+
+ RDICatchPrefetch
+ 1
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 1
+
+
+ CatchNOCPERR
+ 1
+
+
+ CatchCHKERR
+ 1
+
+
+ CatchSTATERR
+ 1
+
+
+ CatchBUSERR
+ 1
+
+
+ CatchINTERR
+ 1
+
+
+ CatchSFERR
+ 1
+
+
+ CatchHARDERR
+ 1
+
+
+ CatchDummy
+ 0
+
+
+ CMSISDAPMultiCPUEnable
+ 0
+
+
+ CMSISDAPMultiCPUNumber
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+
+ CMSISDAPProbeConfigRadio
+ 0
+
+
+ CMSISDAPSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+
+ OCJetEmuParams
+ 1
+
+
+ CCCMSISDAPUsbSerialNo
+
+
+
+ CCCMSISDAPUsbSerialNoSelect
+ 0
+
+
+
+
+ GDBSERVER_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ TCPIP
+ aaa.bbb.ccc.ddd
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJTagBreakpointRadio
+ 0
+
+
+ CCJTagDoUpdateBreakpoints
+ 0
+
+
+ CCJTagUpdateBreakpoints
+ _call_main
+
+
+
+
+ IJET_ID
+ 2
+
+ 9
+ 1
+ 1
+
+ CatchSFERR
+ 1
+
+
+ OCDriverInfo
+ 1
+
+
+ OCIarProbeScriptFile
+ 1
+
+
+ IjetResetList
+ 1
+ 10
+
+
+ IjetHWResetDuration
+ 300
+
+
+ IjetHWResetDelay
+ 200
+
+
+ IjetPowerFromProbe
+ 1
+
+
+ IjetPowerRadio
+ 0
+
+
+ IjetDoLogfile
+ 0
+
+
+ IjetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ IjetInterfaceRadio
+ 0
+
+
+ IjetInterfaceCmdLine
+ 0
+
+
+ IjetMultiTargetEnable
+ 0
+
+
+ IjetMultiTarget
+ 0
+
+
+ IjetScanChainNonARMDevices
+ 0
+
+
+ IjetIRLength
+ 0
+
+
+ IjetJtagSpeedList
+ 0
+ 0
+
+
+ IjetProtocolRadio
+ 0
+
+
+ IjetSwoPin
+ 0
+
+
+ IjetCpuClockEdit
+ 72.0
+
+
+ IjetSwoPrescalerList
+ 1
+ 0
+
+
+ IjetBreakpointRadio
+ 0
+
+
+ IjetRestoreBreakpointsCheck
+ 0
+
+
+ IjetUpdateBreakpointsEdit
+ _call_main
+
+
+ RDICatchReset
+ 0
+
+
+ RDICatchUndef
+ 0
+
+
+ RDICatchSWI
+ 0
+
+
+ RDICatchData
+ 0
+
+
+ RDICatchPrefetch
+ 0
+
+
+ RDICatchIRQ
+ 0
+
+
+ RDICatchFIQ
+ 0
+
+
+ CatchCORERESET
+ 0
+
+
+ CatchMMERR
+ 0
+
+
+ CatchNOCPERR
+ 0
+
+
+ CatchCHKERR
+ 0
+
+
+ CatchSTATERR
+ 0
+
+
+ CatchBUSERR
+ 0
+
+
+ CatchINTERR
+ 0
+
+
+ CatchHARDERR
+ 0
+
+
+ CatchDummy
+ 0
+
+
+ OCProbeCfgOverride
+ 0
+
+
+ OCProbeConfig
+
+
+
+ IjetProbeConfigRadio
+ 0
+
+
+ IjetMultiCPUEnable
+ 0
+
+
+ IjetMultiCPUNumber
+ 0
+
+
+ IjetSelectedCPUBehaviour
+ 0
+
+
+ ICpuName
+
+
+
+ OCJetEmuParams
+ 1
+
+
+ IjetPreferETB
+ 1
+
+
+ IjetTraceSettingsList
+ 0
+ 0
+
+
+ IjetTraceSizeList
+ 0
+ 4
+
+
+ FlashBoardPathSlave
+ 0
+
+
+ CCIjetUsbSerialNo
+
+
+
+ CCIjetUsbSerialNoSelect
+ 0
+
+
+ CatchV8ARReset
+ 0
+
+
+ CatchV8AREREL1NS
+ 0
+
+
+ CatchV8AREREL1S
+ 0
+
+
+ CatchV8AREREL2NS
+ 0
+
+
+ CatchV8AREREL3S
+ 0
+
+
+ CatchV8AREEL1NS
+ 0
+
+
+ CatchV8ARREL1NS
+ 0
+
+
+ CatchV8AREEL1S
+ 0
+
+
+ CatchV8ARREL1S
+ 0
+
+
+ CatchV8AREEL2NS
+ 0
+
+
+ CatchV8ARREL2NS
+ 0
+
+
+ CatchV8AREEL3S
+ 0
+
+
+ CatchV8ARREL3S
+ 0
+
+
+
+
+ JLINK_ID
+ 2
+
+ 16
+ 1
+ 1
+
+ CCCatchSFERR
+ 0
+
+
+ JLinkSpeed
+ 32
+
+
+ CCJLinkDoLogfile
+ 0
+
+
+ CCJLinkLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCJLinkHWResetDelay
+ 0
+
+
+ OCDriverInfo
+ 1
+
+
+ JLinkInitialSpeed
+ 32
+
+
+ CCDoJlinkMultiTarget
+ 0
+
+
+ CCScanChainNonARMDevices
+ 0
+
+
+ CCJLinkMultiTarget
+ 0
+
+
+ CCJLinkIRLength
+ 0
+
+
+ CCJLinkCommRadio
+ 0
+
+
+ CCJLinkTCPIP
+ aaa.bbb.ccc.ddd
+
+
+ CCJLinkSpeedRadioV2
+ 0
+
+
+ CCUSBDevice
+ 1
+ 1
+
+
+ CCRDICatchReset
+ 0
+
+
+ CCRDICatchUndef
+ 0
+
+
+ CCRDICatchSWI
+ 0
+
+
+ CCRDICatchData
+ 0
+
+
+ CCRDICatchPrefetch
+ 0
+
+
+ CCRDICatchIRQ
+ 0
+
+
+ CCRDICatchFIQ
+ 0
+
+
+ CCJLinkBreakpointRadio
+ 0
+
+
+ CCJLinkDoUpdateBreakpoints
+ 0
+
+
+ CCJLinkUpdateBreakpoints
+ _call_main
+
+
+ CCJLinkInterfaceRadio
+ 0
+
+
+ CCJLinkResetList
+ 6
+ 5
+
+
+ CCJLinkInterfaceCmdLine
+ 0
+
+
+ CCCatchCORERESET
+ 0
+
+
+ CCCatchMMERR
+ 0
+
+
+ CCCatchNOCPERR
+ 0
+
+
+ CCCatchCHRERR
+ 0
+
+
+ CCCatchSTATERR
+ 0
+
+
+ CCCatchBUSERR
+ 0
+
+
+ CCCatchINTERR
+ 0
+
+
+ CCCatchHARDERR
+ 0
+
+
+ CCCatchDummy
+ 0
+
+
+ OCJLinkScriptFile
+ 1
+
+
+ CCJLinkUsbSerialNo
+
+
+
+ CCTcpIpAlt
+ 0
+ 0
+
+
+ CCJLinkTcpIpSerialNo
+
+
+
+ CCCpuClockEdit
+ 72.0
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ OCJLinkTraceSource
+ 0
+
+
+ OCJLinkTraceSourceDummy
+ 0
+
+
+ OCJLinkDeviceName
+ 1
+
+
+
+
+ LMIFTDI_ID
+ 2
+
+ 3
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ LmiftdiSpeed
+ 500
+
+
+ CCLmiftdiDoLogfile
+ 0
+
+
+ CCLmiftdiLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCLmiFtdiInterfaceRadio
+ 0
+
+
+ CCLmiFtdiInterfaceCmdLine
+ 0
+
+
+ CCLmiftdiUsbSerialNo
+
+
+
+ CCLmiftdiUsbSerialNoSelect
+ 0
+
+
+ CCLmiftdiResetList
+ 0
+ 0
+
+
+
+
+ NULINK_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+
+
+ PEMICRO_ID
+ 2
+
+ 3
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCJPEMicroShowSettings
+ 0
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+
+
+ STLINK_ID
+ 2
+
+ 8
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCSTLinkInterfaceRadio
+ 0
+
+
+ CCSTLinkInterfaceCmdLine
+ 0
+
+
+ CCSTLinkResetList
+ 3
+ 0
+
+
+ CCCpuClockEdit
+ 72.0
+
+
+ CCSwoClockAuto
+ 0
+
+
+ CCSwoClockEdit
+ 2000
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCSTLinkDoUpdateBreakpoints
+ 0
+
+
+ CCSTLinkUpdateBreakpoints
+ _call_main
+
+
+ CCSTLinkCatchCORERESET
+ 0
+
+
+ CCSTLinkCatchMMERR
+ 0
+
+
+ CCSTLinkCatchNOCPERR
+ 0
+
+
+ CCSTLinkCatchCHRERR
+ 0
+
+
+ CCSTLinkCatchSTATERR
+ 0
+
+
+ CCSTLinkCatchBUSERR
+ 0
+
+
+ CCSTLinkCatchINTERR
+ 0
+
+
+ CCSTLinkCatchSFERR
+ 0
+
+
+ CCSTLinkCatchHARDERR
+ 0
+
+
+ CCSTLinkCatchDummy
+ 0
+
+
+ CCSTLinkUsbSerialNo
+
+
+
+ CCSTLinkUsbSerialNoSelect
+ 0
+
+
+ CCSTLinkJtagSpeedList
+ 2
+ 0
+
+
+ CCSTLinkDAPNumber
+
+
+
+ CCSTLinkDebugAccessPortRadio
+ 0
+
+
+ CCSTLinkUseServerSelect
+ 0
+
+
+ CCSTLinkProbeList
+ 1
+ 0
+
+
+ CCSTLinkTargetVccEnable
+ 1
+
+
+ CCSTLinkTargetVoltage
+ ###Uninitialized###
+
+
+
+
+ THIRDPARTY_ID
+ 2
+
+ 0
+ 1
+ 1
+
+ CThirdPartyDriverDll
+ ###Uninitialized###
+
+
+ CThirdPartyLogFileCheck
+ 0
+
+
+ CThirdPartyLogFileEditB
+ $PROJ_DIR$\cspycomm.log
+
+
+ OCDriverInfo
+ 1
+
+
+
+
+ TIFET_ID
+ 2
+
+ 1
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ CCMSPFetResetList
+ 0
+ 0
+
+
+ CCMSPFetInterfaceRadio
+ 0
+
+
+ CCMSPFetInterfaceCmdLine
+ 0
+
+
+ CCMSPFetTargetVccTypeDefault
+ 0
+
+
+ CCMSPFetTargetVoltage
+ ###Uninitialized###
+
+
+ CCMSPFetVCCDefault
+ 1
+
+
+ CCMSPFetTargetSettlingtime
+ 0
+
+
+ CCMSPFetRadioJtagSpeedType
+ 1
+
+
+ CCMSPFetConnection
+ 0
+ 0
+
+
+ CCMSPFetUsbComPort
+ Automatic
+
+
+ CCMSPFetAllowAccessToBSL
+ 0
+
+
+ CCMSPFetDoLogfile
+ 0
+
+
+ CCMSPFetLogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCMSPFetRadioEraseFlash
+ 1
+
+
+
+
+ XDS100_ID
+ 2
+
+ 9
+ 1
+ 1
+
+ OCDriverInfo
+ 1
+
+
+ TIPackageOverride
+ 0
+
+
+ TIPackage
+
+
+
+ BoardFile
+
+
+
+ DoLogfile
+ 0
+
+
+ LogFile
+ $PROJ_DIR$\cspycomm.log
+
+
+ CCXds100BreakpointRadio
+ 0
+
+
+ CCXds100DoUpdateBreakpoints
+ 0
+
+
+ CCXds100UpdateBreakpoints
+ _call_main
+
+
+ CCXds100CatchReset
+ 0
+
+
+ CCXds100CatchUndef
+ 0
+
+
+ CCXds100CatchSWI
+ 0
+
+
+ CCXds100CatchData
+ 0
+
+
+ CCXds100CatchPrefetch
+ 0
+
+
+ CCXds100CatchIRQ
+ 0
+
+
+ CCXds100CatchFIQ
+ 0
+
+
+ CCXds100CatchCORERESET
+ 0
+
+
+ CCXds100CatchMMERR
+ 0
+
+
+ CCXds100CatchNOCPERR
+ 0
+
+
+ CCXds100CatchCHRERR
+ 0
+
+
+ CCXds100CatchSTATERR
+ 0
+
+
+ CCXds100CatchBUSERR
+ 0
+
+
+ CCXds100CatchINTERR
+ 0
+
+
+ CCXds100CatchSFERR
+ 0
+
+
+ CCXds100CatchHARDERR
+ 0
+
+
+ CCXds100CatchDummy
+ 0
+
+
+ CCXds100CpuClockEdit
+
+
+
+ CCXds100SwoClockAuto
+ 0
+
+
+ CCXds100SwoClockEdit
+ 1000
+
+
+ CCXds100HWResetDelay
+ 0
+
+
+ CCXds100ResetList
+ 1
+ 0
+
+
+ CCXds100UsbSerialNo
+
+
+
+ CCXds100UsbSerialNoSelect
+ 0
+
+
+ CCXds100JtagSpeedList
+ 0
+ 0
+
+
+ CCXds100InterfaceRadio
+ 0
+
+
+ CCXds100InterfaceCmdLine
+ 0
+
+
+ CCXds100ProbeList
+ 0
+ 0
+
+
+ CCXds100SWOPortRadio
+ 0
+
+
+ CCXds100SWOPort
+ 1
+
+
+ CCXDSTargetVccEnable
+ 0
+
+
+ CCXDSTargetVoltage
+ ###Uninitialized###
+
+
+ OCXDSDigitalStatesConfigFile
+ 1
+
+
+ OCSelectedCoreName
+ 1
+
+
+
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+ 0
+
+
+ $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+ 0
+
+
+ $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+ 0
+
+
+
+
diff --git a/lesson-03/simulator-iar/lesson.ewp b/lesson-03/simulator-iar/project.ewp
similarity index 50%
rename from lesson-03/simulator-iar/lesson.ewp
rename to lesson-03/simulator-iar/project.ewp
index 4d240b8..6475c8c 100644
--- a/lesson-03/simulator-iar/lesson.ewp
+++ b/lesson-03/simulator-iar/project.ewp
@@ -14,18 +14,10 @@
35
1
1
-
- FPU64
- 1
-
BrowseInfoPath
Debug\BrowseInfo
-
- OGProductVersion
- 9.30.1.0
-
ExePath
Debug\Exe
@@ -72,6 +64,10 @@
RTDescription
A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
+
+ OGProductVersion
+ 5.10.0.159
+
OGLastSavedByProductVersion
9.32.1.54977
@@ -103,7 +99,7 @@
GBECoreSlave
32
- 38
+ 39
OGUseCmsis
@@ -184,7 +180,7 @@
DSPExtension
- 0
+ 1
TrustZone
@@ -211,6 +207,10 @@
PointerAuthentication
0
+
+ FPU64
+ 1
+
@@ -591,7 +591,7 @@
AOutputFile
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+ $FILE_BNAME$.o
ALimitErrorsCheck
@@ -645,7 +645,7 @@
OOCOutputFile
-
+ c.srec
OOCCommandLineProducer
@@ -684,7 +684,7 @@
1
IlinkOutputFile
- $PROJ_FNAME$.out
+ c.out
IlinkLibIOConfig
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IlinkMapFile
- 1
+ 0
IlinkLogFile
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IlinkIcfFile
-
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IlinkIcfFileSlave
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diff --git a/lesson-03/simulator-iar/workspace.eww b/lesson-03/simulator-iar/workspace.eww
new file mode 100644
index 0000000..faa93f3
--- /dev/null
+++ b/lesson-03/simulator-iar/workspace.eww
@@ -0,0 +1,10 @@
+
+
+
+
+ $WS_DIR$\project.ewp
+
+
+
+
+
diff --git a/lesson-04/tm4c123-iar/project.ewp b/lesson-04/tm4c123-iar/project.ewp
index 5dcc3da..761fe75 100644
--- a/lesson-04/tm4c123-iar/project.ewp
+++ b/lesson-04/tm4c123-iar/project.ewp
@@ -16,19 +16,19 @@
1
BrowseInfoPath
- Debug\BrowseInfo
+ dbg
ExePath
- Debug\Exe
+ dbg
ObjPath
- Debug\Obj
+ dbg
ListPath
- Debug\List
+ dbg
GEndianMode
@@ -62,7 +62,7 @@
RTDescription
- Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
+ A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
OGProductVersion
@@ -201,7 +201,7 @@
BuildFilesPath
- Debug
+ dbg
PointerAuthentication
diff --git a/lesson-05/tm4c123-iar/project.ewd b/lesson-05/tm4c123-iar/project.ewd
index 60712cf..88d8748 100644
--- a/lesson-05/tm4c123-iar/project.ewd
+++ b/lesson-05/tm4c123-iar/project.ewd
@@ -44,7 +44,7 @@
MemFile
- $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\LM4F120H5QR.ddf
+ $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf
RunToEnable
@@ -112,7 +112,7 @@
FlashLoadersV3
- $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashLM4FxxxHxx.board
+ $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashTC4_H6_o.board
OCImagesSuppressCheck1
@@ -1188,7 +1188,7 @@
CCSTLinkProbeList
1
- 0
+ 2
CCSTLinkTargetVccEnable
diff --git a/lesson-05/tm4c123-iar/project.ewp b/lesson-05/tm4c123-iar/project.ewp
index f6ed365..afe4ee9 100644
--- a/lesson-05/tm4c123-iar/project.ewp
+++ b/lesson-05/tm4c123-iar/project.ewp
@@ -16,19 +16,19 @@
1
BrowseInfoPath
- Debug\BrowseInfo
+ dbg
ExePath
- Debug\Exe
+ dbg
ObjPath
- Debug\Obj
+ dbg
ListPath
- Debug\List
+ dbg
GEndianMode
@@ -36,11 +36,11 @@
Input description
- Full formatting.
+ Full formatting, without multibyte support.
Output description
- Full formatting.
+ Full formatting, without multibyte support.
GOutputBinary
@@ -62,7 +62,7 @@
RTDescription
- Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
+ A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
OGProductVersion
@@ -74,7 +74,7 @@
OGChipSelectEditMenu
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
GenLowLevelInterface
@@ -99,7 +99,7 @@
GBECoreSlave
32
- 40
+ 39
OGUseCmsis
@@ -120,7 +120,7 @@
GFPUDeviceSlave
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
FPU2
@@ -201,7 +201,7 @@
BuildFilesPath
- Debug
+ dbg
PointerAuthentication
@@ -287,7 +287,7 @@
CCAllowList
1
- 11111110
+ 10010100
CCDebugInfo
@@ -363,7 +363,7 @@
CCOptLevel
- 3
+ 2
CCOptStrategy
@@ -372,7 +372,7 @@
CCOptLevelSlave
- 3
+ 2
CCPosIndRopi
@@ -637,7 +637,7 @@
OOCOutputFormat
3
- 0
+ 3
OCOutputOverride
@@ -645,7 +645,7 @@
OOCOutputFile
- c.srec
+ project.bin
OOCCommandLineProducer
@@ -653,7 +653,7 @@
OOCObjCopyEnable
- 0
+ 1
@@ -756,7 +756,7 @@
IlinkIcfFile
- $TOOLKIT_DIR$\config\linker\TexasInstruments\LM4F120H5QR.icf
+ $TOOLKIT_DIR$\config\linker\TexasInstruments\TM4C123GH6.icf
IlinkIcfFileSlave
@@ -1077,9 +1077,9 @@
- $PROJ_DIR$\lm4f120h5qr.h
+ $PROJ_DIR$\main.c
- $PROJ_DIR$\main.c
+ $PROJ_DIR$\tm4c.h
diff --git a/lesson-06/tm4c123-iar/lm4f120h5qr.h b/lesson-06/tm4c123-iar/lm4f120h5qr.h
deleted file mode 100644
index 0a01508..0000000
--- a/lesson-06/tm4c123-iar/lm4f120h5qr.h
+++ /dev/null
@@ -1,10025 +0,0 @@
-//*****************************************************************************
-//
-// lm4f120h5qr.h - LM4F120H5QR Register Definitions
-//
-// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
-// Software License Agreement
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-//
-// Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the
-// distribution.
-//
-// Neither the name of Texas Instruments Incorporated nor the names of
-// its contributors may be used to endorse or promote products derived
-// from this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// This is part of revision 9453 of the Stellaris Firmware Development Package.
-//
-//*****************************************************************************
-
-#ifndef __LM4F120H5QR_H__
-#define __LM4F120H5QR_H__
-
-//*****************************************************************************
-//
-// Watchdog Timer registers (WATCHDOG0)
-//
-//*****************************************************************************
-#define WATCHDOG0_LOAD_R (*((volatile unsigned long *)0x40000000))
-#define WATCHDOG0_VALUE_R (*((volatile unsigned long *)0x40000004))
-#define WATCHDOG0_CTL_R (*((volatile unsigned long *)0x40000008))
-#define WATCHDOG0_ICR_R (*((volatile unsigned long *)0x4000000C))
-#define WATCHDOG0_RIS_R (*((volatile unsigned long *)0x40000010))
-#define WATCHDOG0_MIS_R (*((volatile unsigned long *)0x40000014))
-#define WATCHDOG0_TEST_R (*((volatile unsigned long *)0x40000418))
-#define WATCHDOG0_LOCK_R (*((volatile unsigned long *)0x40000C00))
-
-//*****************************************************************************
-//
-// Watchdog Timer registers (WATCHDOG1)
-//
-//*****************************************************************************
-#define WATCHDOG1_LOAD_R (*((volatile unsigned long *)0x40001000))
-#define WATCHDOG1_VALUE_R (*((volatile unsigned long *)0x40001004))
-#define WATCHDOG1_CTL_R (*((volatile unsigned long *)0x40001008))
-#define WATCHDOG1_ICR_R (*((volatile unsigned long *)0x4000100C))
-#define WATCHDOG1_RIS_R (*((volatile unsigned long *)0x40001010))
-#define WATCHDOG1_MIS_R (*((volatile unsigned long *)0x40001014))
-#define WATCHDOG1_TEST_R (*((volatile unsigned long *)0x40001418))
-#define WATCHDOG1_LOCK_R (*((volatile unsigned long *)0x40001C00))
-
-//*****************************************************************************
-//
-// GPIO registers (PORTA)
-//
-//*****************************************************************************
-#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000)
-#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC))
-#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400))
-#define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404))
-#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408))
-#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C))
-#define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410))
-#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414))
-#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418))
-#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C))
-#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420))
-#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500))
-#define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504))
-#define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508))
-#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C))
-#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510))
-#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514))
-#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518))
-#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C))
-#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520))
-#define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524))
-#define GPIO_PORTA_AMSEL_R (*((volatile unsigned long *)0x40004528))
-#define GPIO_PORTA_PCTL_R (*((volatile unsigned long *)0x4000452C))
-#define GPIO_PORTA_ADCCTL_R (*((volatile unsigned long *)0x40004530))
-#define GPIO_PORTA_DMACTL_R (*((volatile unsigned long *)0x40004534))
-#define GPIO_PORTA_SI_R (*((volatile unsigned long *)0x40004538))
-
-//*****************************************************************************
-//
-// GPIO registers (PORTB)
-//
-//*****************************************************************************
-#define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000)
-#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC))
-#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400))
-#define GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404))
-#define GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408))
-#define GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C))
-#define GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410))
-#define GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414))
-#define GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418))
-#define GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C))
-#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420))
-#define GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500))
-#define GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504))
-#define GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508))
-#define GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C))
-#define GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510))
-#define GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514))
-#define GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518))
-#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C))
-#define GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520))
-#define GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524))
-#define GPIO_PORTB_AMSEL_R (*((volatile unsigned long *)0x40005528))
-#define GPIO_PORTB_PCTL_R (*((volatile unsigned long *)0x4000552C))
-#define GPIO_PORTB_ADCCTL_R (*((volatile unsigned long *)0x40005530))
-#define GPIO_PORTB_DMACTL_R (*((volatile unsigned long *)0x40005534))
-#define GPIO_PORTB_SI_R (*((volatile unsigned long *)0x40005538))
-
-//*****************************************************************************
-//
-// GPIO registers (PORTC)
-//
-//*****************************************************************************
-#define GPIO_PORTC_DATA_BITS_R ((volatile unsigned long *)0x40006000)
-#define GPIO_PORTC_DATA_R (*((volatile unsigned long *)0x400063FC))
-#define GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400))
-#define GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404))
-#define GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408))
-#define GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C))
-#define GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410))
-#define GPIO_PORTC_RIS_R (*((volatile unsigned long *)0x40006414))
-#define GPIO_PORTC_MIS_R (*((volatile unsigned long *)0x40006418))
-#define GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C))
-#define GPIO_PORTC_AFSEL_R (*((volatile unsigned long *)0x40006420))
-#define GPIO_PORTC_DR2R_R (*((volatile unsigned long *)0x40006500))
-#define GPIO_PORTC_DR4R_R (*((volatile unsigned long *)0x40006504))
-#define GPIO_PORTC_DR8R_R (*((volatile unsigned long *)0x40006508))
-#define GPIO_PORTC_ODR_R (*((volatile unsigned long *)0x4000650C))
-#define GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510))
-#define GPIO_PORTC_PDR_R (*((volatile unsigned long *)0x40006514))
-#define GPIO_PORTC_SLR_R (*((volatile unsigned long *)0x40006518))
-#define GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C))
-#define GPIO_PORTC_LOCK_R (*((volatile unsigned long *)0x40006520))
-#define GPIO_PORTC_CR_R (*((volatile unsigned long *)0x40006524))
-#define GPIO_PORTC_AMSEL_R (*((volatile unsigned long *)0x40006528))
-#define GPIO_PORTC_PCTL_R (*((volatile unsigned long *)0x4000652C))
-#define GPIO_PORTC_ADCCTL_R (*((volatile unsigned long *)0x40006530))
-#define GPIO_PORTC_DMACTL_R (*((volatile unsigned long *)0x40006534))
-#define GPIO_PORTC_SI_R (*((volatile unsigned long *)0x40006538))
-
-//*****************************************************************************
-//
-// GPIO registers (PORTD)
-//
-//*****************************************************************************
-#define GPIO_PORTD_DATA_BITS_R ((volatile unsigned long *)0x40007000)
-#define GPIO_PORTD_DATA_R (*((volatile unsigned long *)0x400073FC))
-#define GPIO_PORTD_DIR_R (*((volatile unsigned long *)0x40007400))
-#define GPIO_PORTD_IS_R (*((volatile unsigned long *)0x40007404))
-#define GPIO_PORTD_IBE_R (*((volatile unsigned long *)0x40007408))
-#define GPIO_PORTD_IEV_R (*((volatile unsigned long *)0x4000740C))
-#define GPIO_PORTD_IM_R (*((volatile unsigned long *)0x40007410))
-#define GPIO_PORTD_RIS_R (*((volatile unsigned long *)0x40007414))
-#define GPIO_PORTD_MIS_R (*((volatile unsigned long *)0x40007418))
-#define GPIO_PORTD_ICR_R (*((volatile unsigned long *)0x4000741C))
-#define GPIO_PORTD_AFSEL_R (*((volatile unsigned long *)0x40007420))
-#define GPIO_PORTD_DR2R_R (*((volatile unsigned long *)0x40007500))
-#define GPIO_PORTD_DR4R_R (*((volatile unsigned long *)0x40007504))
-#define GPIO_PORTD_DR8R_R (*((volatile unsigned long *)0x40007508))
-#define GPIO_PORTD_ODR_R (*((volatile unsigned long *)0x4000750C))
-#define GPIO_PORTD_PUR_R (*((volatile unsigned long *)0x40007510))
-#define GPIO_PORTD_PDR_R (*((volatile unsigned long *)0x40007514))
-#define GPIO_PORTD_SLR_R (*((volatile unsigned long *)0x40007518))
-#define GPIO_PORTD_DEN_R (*((volatile unsigned long *)0x4000751C))
-#define GPIO_PORTD_LOCK_R (*((volatile unsigned long *)0x40007520))
-#define GPIO_PORTD_CR_R (*((volatile unsigned long *)0x40007524))
-#define GPIO_PORTD_AMSEL_R (*((volatile unsigned long *)0x40007528))
-#define GPIO_PORTD_PCTL_R (*((volatile unsigned long *)0x4000752C))
-#define GPIO_PORTD_ADCCTL_R (*((volatile unsigned long *)0x40007530))
-#define GPIO_PORTD_DMACTL_R (*((volatile unsigned long *)0x40007534))
-#define GPIO_PORTD_SI_R (*((volatile unsigned long *)0x40007538))
-
-//*****************************************************************************
-//
-// SSI registers (SSI0)
-//
-//*****************************************************************************
-#define SSI0_CR0_R (*((volatile unsigned long *)0x40008000))
-#define SSI0_CR1_R (*((volatile unsigned long *)0x40008004))
-#define SSI0_DR_R (*((volatile unsigned long *)0x40008008))
-#define SSI0_SR_R (*((volatile unsigned long *)0x4000800C))
-#define SSI0_CPSR_R (*((volatile unsigned long *)0x40008010))
-#define SSI0_IM_R (*((volatile unsigned long *)0x40008014))
-#define SSI0_RIS_R (*((volatile unsigned long *)0x40008018))
-#define SSI0_MIS_R (*((volatile unsigned long *)0x4000801C))
-#define SSI0_ICR_R (*((volatile unsigned long *)0x40008020))
-#define SSI0_DMACTL_R (*((volatile unsigned long *)0x40008024))
-#define SSI0_CC_R (*((volatile unsigned long *)0x40008FC8))
-
-//*****************************************************************************
-//
-// SSI registers (SSI1)
-//
-//*****************************************************************************
-#define SSI1_CR0_R (*((volatile unsigned long *)0x40009000))
-#define SSI1_CR1_R (*((volatile unsigned long *)0x40009004))
-#define SSI1_DR_R (*((volatile unsigned long *)0x40009008))
-#define SSI1_SR_R (*((volatile unsigned long *)0x4000900C))
-#define SSI1_CPSR_R (*((volatile unsigned long *)0x40009010))
-#define SSI1_IM_R (*((volatile unsigned long *)0x40009014))
-#define SSI1_RIS_R (*((volatile unsigned long *)0x40009018))
-#define SSI1_MIS_R (*((volatile unsigned long *)0x4000901C))
-#define SSI1_ICR_R (*((volatile unsigned long *)0x40009020))
-#define SSI1_DMACTL_R (*((volatile unsigned long *)0x40009024))
-#define SSI1_CC_R (*((volatile unsigned long *)0x40009FC8))
-
-//*****************************************************************************
-//
-// SSI registers (SSI2)
-//
-//*****************************************************************************
-#define SSI2_CR0_R (*((volatile unsigned long *)0x4000A000))
-#define SSI2_CR1_R (*((volatile unsigned long *)0x4000A004))
-#define SSI2_DR_R (*((volatile unsigned long *)0x4000A008))
-#define SSI2_SR_R (*((volatile unsigned long *)0x4000A00C))
-#define SSI2_CPSR_R (*((volatile unsigned long *)0x4000A010))
-#define SSI2_IM_R (*((volatile unsigned long *)0x4000A014))
-#define SSI2_RIS_R (*((volatile unsigned long *)0x4000A018))
-#define SSI2_MIS_R (*((volatile unsigned long *)0x4000A01C))
-#define SSI2_ICR_R (*((volatile unsigned long *)0x4000A020))
-#define SSI2_DMACTL_R (*((volatile unsigned long *)0x4000A024))
-#define SSI2_CC_R (*((volatile unsigned long *)0x4000AFC8))
-
-//*****************************************************************************
-//
-// SSI registers (SSI3)
-//
-//*****************************************************************************
-#define SSI3_CR0_R (*((volatile unsigned long *)0x4000B000))
-#define SSI3_CR1_R (*((volatile unsigned long *)0x4000B004))
-#define SSI3_DR_R (*((volatile unsigned long *)0x4000B008))
-#define SSI3_SR_R (*((volatile unsigned long *)0x4000B00C))
-#define SSI3_CPSR_R (*((volatile unsigned long *)0x4000B010))
-#define SSI3_IM_R (*((volatile unsigned long *)0x4000B014))
-#define SSI3_RIS_R (*((volatile unsigned long *)0x4000B018))
-#define SSI3_MIS_R (*((volatile unsigned long *)0x4000B01C))
-#define SSI3_ICR_R (*((volatile unsigned long *)0x4000B020))
-#define SSI3_DMACTL_R (*((volatile unsigned long *)0x4000B024))
-#define SSI3_CC_R (*((volatile unsigned long *)0x4000BFC8))
-
-//*****************************************************************************
-//
-// UART registers (UART0)
-//
-//*****************************************************************************
-#define UART0_DR_R (*((volatile unsigned long *)0x4000C000))
-#define UART0_RSR_R (*((volatile unsigned long *)0x4000C004))
-#define UART0_ECR_R (*((volatile unsigned long *)0x4000C004))
-#define UART0_FR_R (*((volatile unsigned long *)0x4000C018))
-#define UART0_ILPR_R (*((volatile unsigned long *)0x4000C020))
-#define UART0_IBRD_R (*((volatile unsigned long *)0x4000C024))
-#define UART0_FBRD_R (*((volatile unsigned long *)0x4000C028))
-#define UART0_LCRH_R (*((volatile unsigned long *)0x4000C02C))
-#define UART0_CTL_R (*((volatile unsigned long *)0x4000C030))
-#define UART0_IFLS_R (*((volatile unsigned long *)0x4000C034))
-#define UART0_IM_R (*((volatile unsigned long *)0x4000C038))
-#define UART0_RIS_R (*((volatile unsigned long *)0x4000C03C))
-#define UART0_MIS_R (*((volatile unsigned long *)0x4000C040))
-#define UART0_ICR_R (*((volatile unsigned long *)0x4000C044))
-#define UART0_DMACTL_R (*((volatile unsigned long *)0x4000C048))
-#define UART0_LCTL_R (*((volatile unsigned long *)0x4000C090))
-#define UART0_LSS_R (*((volatile unsigned long *)0x4000C094))
-#define UART0_LTIM_R (*((volatile unsigned long *)0x4000C098))
-#define UART0_9BITADDR_R (*((volatile unsigned long *)0x4000C0A4))
-#define UART0_9BITAMASK_R (*((volatile unsigned long *)0x4000C0A8))
-#define UART0_PP_R (*((volatile unsigned long *)0x4000CFC0))
-#define UART0_CC_R (*((volatile unsigned long *)0x4000CFC8))
-
-//*****************************************************************************
-//
-// UART registers (UART1)
-//
-//*****************************************************************************
-#define UART1_DR_R (*((volatile unsigned long *)0x4000D000))
-#define UART1_RSR_R (*((volatile unsigned long *)0x4000D004))
-#define UART1_ECR_R (*((volatile unsigned long *)0x4000D004))
-#define UART1_FR_R (*((volatile unsigned long *)0x4000D018))
-#define UART1_ILPR_R (*((volatile unsigned long *)0x4000D020))
-#define UART1_IBRD_R (*((volatile unsigned long *)0x4000D024))
-#define UART1_FBRD_R (*((volatile unsigned long *)0x4000D028))
-#define UART1_LCRH_R (*((volatile unsigned long *)0x4000D02C))
-#define UART1_CTL_R (*((volatile unsigned long *)0x4000D030))
-#define UART1_IFLS_R (*((volatile unsigned long *)0x4000D034))
-#define UART1_IM_R (*((volatile unsigned long *)0x4000D038))
-#define UART1_RIS_R (*((volatile unsigned long *)0x4000D03C))
-#define UART1_MIS_R (*((volatile unsigned long *)0x4000D040))
-#define UART1_ICR_R (*((volatile unsigned long *)0x4000D044))
-#define UART1_DMACTL_R (*((volatile unsigned long *)0x4000D048))
-#define UART1_LCTL_R (*((volatile unsigned long *)0x4000D090))
-#define UART1_LSS_R (*((volatile unsigned long *)0x4000D094))
-#define UART1_LTIM_R (*((volatile unsigned long *)0x4000D098))
-#define UART1_9BITADDR_R (*((volatile unsigned long *)0x4000D0A4))
-#define UART1_9BITAMASK_R (*((volatile unsigned long *)0x4000D0A8))
-#define UART1_PP_R (*((volatile unsigned long *)0x4000DFC0))
-#define UART1_CC_R (*((volatile unsigned long *)0x4000DFC8))
-
-//*****************************************************************************
-//
-// UART registers (UART2)
-//
-//*****************************************************************************
-#define UART2_DR_R (*((volatile unsigned long *)0x4000E000))
-#define UART2_RSR_R (*((volatile unsigned long *)0x4000E004))
-#define UART2_ECR_R (*((volatile unsigned long *)0x4000E004))
-#define UART2_FR_R (*((volatile unsigned long *)0x4000E018))
-#define UART2_ILPR_R (*((volatile unsigned long *)0x4000E020))
-#define UART2_IBRD_R (*((volatile unsigned long *)0x4000E024))
-#define UART2_FBRD_R (*((volatile unsigned long *)0x4000E028))
-#define UART2_LCRH_R (*((volatile unsigned long *)0x4000E02C))
-#define UART2_CTL_R (*((volatile unsigned long *)0x4000E030))
-#define UART2_IFLS_R (*((volatile unsigned long *)0x4000E034))
-#define UART2_IM_R (*((volatile unsigned long *)0x4000E038))
-#define UART2_RIS_R (*((volatile unsigned long *)0x4000E03C))
-#define UART2_MIS_R (*((volatile unsigned long *)0x4000E040))
-#define UART2_ICR_R (*((volatile unsigned long *)0x4000E044))
-#define UART2_DMACTL_R (*((volatile unsigned long *)0x4000E048))
-#define UART2_LCTL_R (*((volatile unsigned long *)0x4000E090))
-#define UART2_LSS_R (*((volatile unsigned long *)0x4000E094))
-#define UART2_LTIM_R (*((volatile unsigned long *)0x4000E098))
-#define UART2_9BITADDR_R (*((volatile unsigned long *)0x4000E0A4))
-#define UART2_9BITAMASK_R (*((volatile unsigned long *)0x4000E0A8))
-#define UART2_PP_R (*((volatile unsigned long *)0x4000EFC0))
-#define UART2_CC_R (*((volatile unsigned long *)0x4000EFC8))
-
-//*****************************************************************************
-//
-// UART registers (UART3)
-//
-//*****************************************************************************
-#define UART3_DR_R (*((volatile unsigned long *)0x4000F000))
-#define UART3_RSR_R (*((volatile unsigned long *)0x4000F004))
-#define UART3_ECR_R (*((volatile unsigned long *)0x4000F004))
-#define UART3_FR_R (*((volatile unsigned long *)0x4000F018))
-#define UART3_ILPR_R (*((volatile unsigned long *)0x4000F020))
-#define UART3_IBRD_R (*((volatile unsigned long *)0x4000F024))
-#define UART3_FBRD_R (*((volatile unsigned long *)0x4000F028))
-#define UART3_LCRH_R (*((volatile unsigned long *)0x4000F02C))
-#define UART3_CTL_R (*((volatile unsigned long *)0x4000F030))
-#define UART3_IFLS_R (*((volatile unsigned long *)0x4000F034))
-#define UART3_IM_R (*((volatile unsigned long *)0x4000F038))
-#define UART3_RIS_R (*((volatile unsigned long *)0x4000F03C))
-#define UART3_MIS_R (*((volatile unsigned long *)0x4000F040))
-#define UART3_ICR_R (*((volatile unsigned long *)0x4000F044))
-#define UART3_DMACTL_R (*((volatile unsigned long *)0x4000F048))
-#define UART3_LCTL_R (*((volatile unsigned long *)0x4000F090))
-#define UART3_LSS_R (*((volatile unsigned long *)0x4000F094))
-#define UART3_LTIM_R (*((volatile unsigned long *)0x4000F098))
-#define UART3_9BITADDR_R (*((volatile unsigned long *)0x4000F0A4))
-#define UART3_9BITAMASK_R (*((volatile unsigned long *)0x4000F0A8))
-#define UART3_PP_R (*((volatile unsigned long *)0x4000FFC0))
-#define UART3_CC_R (*((volatile unsigned long *)0x4000FFC8))
-
-//*****************************************************************************
-//
-// UART registers (UART4)
-//
-//*****************************************************************************
-#define UART4_DR_R (*((volatile unsigned long *)0x40010000))
-#define UART4_RSR_R (*((volatile unsigned long *)0x40010004))
-#define UART4_ECR_R (*((volatile unsigned long *)0x40010004))
-#define UART4_FR_R (*((volatile unsigned long *)0x40010018))
-#define UART4_ILPR_R (*((volatile unsigned long *)0x40010020))
-#define UART4_IBRD_R (*((volatile unsigned long *)0x40010024))
-#define UART4_FBRD_R (*((volatile unsigned long *)0x40010028))
-#define UART4_LCRH_R (*((volatile unsigned long *)0x4001002C))
-#define UART4_CTL_R (*((volatile unsigned long *)0x40010030))
-#define UART4_IFLS_R (*((volatile unsigned long *)0x40010034))
-#define UART4_IM_R (*((volatile unsigned long *)0x40010038))
-#define UART4_RIS_R (*((volatile unsigned long *)0x4001003C))
-#define UART4_MIS_R (*((volatile unsigned long *)0x40010040))
-#define UART4_ICR_R (*((volatile unsigned long *)0x40010044))
-#define UART4_DMACTL_R (*((volatile unsigned long *)0x40010048))
-#define UART4_LCTL_R (*((volatile unsigned long *)0x40010090))
-#define UART4_LSS_R (*((volatile unsigned long *)0x40010094))
-#define UART4_LTIM_R (*((volatile unsigned long *)0x40010098))
-#define UART4_9BITADDR_R (*((volatile unsigned long *)0x400100A4))
-#define UART4_9BITAMASK_R (*((volatile unsigned long *)0x400100A8))
-#define UART4_PP_R (*((volatile unsigned long *)0x40010FC0))
-#define UART4_CC_R (*((volatile unsigned long *)0x40010FC8))
-
-//*****************************************************************************
-//
-// UART registers (UART5)
-//
-//*****************************************************************************
-#define UART5_DR_R (*((volatile unsigned long *)0x40011000))
-#define UART5_RSR_R (*((volatile unsigned long *)0x40011004))
-#define UART5_ECR_R (*((volatile unsigned long *)0x40011004))
-#define UART5_FR_R (*((volatile unsigned long *)0x40011018))
-#define UART5_ILPR_R (*((volatile unsigned long *)0x40011020))
-#define UART5_IBRD_R (*((volatile unsigned long *)0x40011024))
-#define UART5_FBRD_R (*((volatile unsigned long *)0x40011028))
-#define UART5_LCRH_R (*((volatile unsigned long *)0x4001102C))
-#define UART5_CTL_R (*((volatile unsigned long *)0x40011030))
-#define UART5_IFLS_R (*((volatile unsigned long *)0x40011034))
-#define UART5_IM_R (*((volatile unsigned long *)0x40011038))
-#define UART5_RIS_R (*((volatile unsigned long *)0x4001103C))
-#define UART5_MIS_R (*((volatile unsigned long *)0x40011040))
-#define UART5_ICR_R (*((volatile unsigned long *)0x40011044))
-#define UART5_DMACTL_R (*((volatile unsigned long *)0x40011048))
-#define UART5_LCTL_R (*((volatile unsigned long *)0x40011090))
-#define UART5_LSS_R (*((volatile unsigned long *)0x40011094))
-#define UART5_LTIM_R (*((volatile unsigned long *)0x40011098))
-#define UART5_9BITADDR_R (*((volatile unsigned long *)0x400110A4))
-#define UART5_9BITAMASK_R (*((volatile unsigned long *)0x400110A8))
-#define UART5_PP_R (*((volatile unsigned long *)0x40011FC0))
-#define UART5_CC_R (*((volatile unsigned long *)0x40011FC8))
-
-//*****************************************************************************
-//
-// UART registers (UART6)
-//
-//*****************************************************************************
-#define UART6_DR_R (*((volatile unsigned long *)0x40012000))
-#define UART6_RSR_R (*((volatile unsigned long *)0x40012004))
-#define UART6_ECR_R (*((volatile unsigned long *)0x40012004))
-#define UART6_FR_R (*((volatile unsigned long *)0x40012018))
-#define UART6_ILPR_R (*((volatile unsigned long *)0x40012020))
-#define UART6_IBRD_R (*((volatile unsigned long *)0x40012024))
-#define UART6_FBRD_R (*((volatile unsigned long *)0x40012028))
-#define UART6_LCRH_R (*((volatile unsigned long *)0x4001202C))
-#define UART6_CTL_R (*((volatile unsigned long *)0x40012030))
-#define UART6_IFLS_R (*((volatile unsigned long *)0x40012034))
-#define UART6_IM_R (*((volatile unsigned long *)0x40012038))
-#define UART6_RIS_R (*((volatile unsigned long *)0x4001203C))
-#define UART6_MIS_R (*((volatile unsigned long *)0x40012040))
-#define UART6_ICR_R (*((volatile unsigned long *)0x40012044))
-#define UART6_DMACTL_R (*((volatile unsigned long *)0x40012048))
-#define UART6_LCTL_R (*((volatile unsigned long *)0x40012090))
-#define UART6_LSS_R (*((volatile unsigned long *)0x40012094))
-#define UART6_LTIM_R (*((volatile unsigned long *)0x40012098))
-#define UART6_9BITADDR_R (*((volatile unsigned long *)0x400120A4))
-#define UART6_9BITAMASK_R (*((volatile unsigned long *)0x400120A8))
-#define UART6_PP_R (*((volatile unsigned long *)0x40012FC0))
-#define UART6_CC_R (*((volatile unsigned long *)0x40012FC8))
-
-//*****************************************************************************
-//
-// UART registers (UART7)
-//
-//*****************************************************************************
-#define UART7_DR_R (*((volatile unsigned long *)0x40013000))
-#define UART7_RSR_R (*((volatile unsigned long *)0x40013004))
-#define UART7_ECR_R (*((volatile unsigned long *)0x40013004))
-#define UART7_FR_R (*((volatile unsigned long *)0x40013018))
-#define UART7_ILPR_R (*((volatile unsigned long *)0x40013020))
-#define UART7_IBRD_R (*((volatile unsigned long *)0x40013024))
-#define UART7_FBRD_R (*((volatile unsigned long *)0x40013028))
-#define UART7_LCRH_R (*((volatile unsigned long *)0x4001302C))
-#define UART7_CTL_R (*((volatile unsigned long *)0x40013030))
-#define UART7_IFLS_R (*((volatile unsigned long *)0x40013034))
-#define UART7_IM_R (*((volatile unsigned long *)0x40013038))
-#define UART7_RIS_R (*((volatile unsigned long *)0x4001303C))
-#define UART7_MIS_R (*((volatile unsigned long *)0x40013040))
-#define UART7_ICR_R (*((volatile unsigned long *)0x40013044))
-#define UART7_DMACTL_R (*((volatile unsigned long *)0x40013048))
-#define UART7_LCTL_R (*((volatile unsigned long *)0x40013090))
-#define UART7_LSS_R (*((volatile unsigned long *)0x40013094))
-#define UART7_LTIM_R (*((volatile unsigned long *)0x40013098))
-#define UART7_9BITADDR_R (*((volatile unsigned long *)0x400130A4))
-#define UART7_9BITAMASK_R (*((volatile unsigned long *)0x400130A8))
-#define UART7_PP_R (*((volatile unsigned long *)0x40013FC0))
-#define UART7_CC_R (*((volatile unsigned long *)0x40013FC8))
-
-//*****************************************************************************
-//
-// I2C registers (I2C0 MASTER)
-//
-//*****************************************************************************
-#define I2C0_MASTER_MSA_R (*((volatile unsigned long *)0x40020000))
-#define I2C0_MASTER_MCS_R (*((volatile unsigned long *)0x40020004))
-#define I2C0_MASTER_MDR_R (*((volatile unsigned long *)0x40020008))
-#define I2C0_MASTER_MTPR_R (*((volatile unsigned long *)0x4002000C))
-#define I2C0_MASTER_MIMR_R (*((volatile unsigned long *)0x40020010))
-#define I2C0_MASTER_MRIS_R (*((volatile unsigned long *)0x40020014))
-#define I2C0_MASTER_MMIS_R (*((volatile unsigned long *)0x40020018))
-#define I2C0_MASTER_MICR_R (*((volatile unsigned long *)0x4002001C))
-#define I2C0_MASTER_MCR_R (*((volatile unsigned long *)0x40020020))
-#define I2C0_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40020024))
-#define I2C0_MASTER_MBMON_R (*((volatile unsigned long *)0x4002002C))
-
-//*****************************************************************************
-//
-// I2C registers (I2C0 SLAVE)
-//
-//*****************************************************************************
-#define I2C0_SLAVE_SOAR_R (*((volatile unsigned long *)0x40020800))
-#define I2C0_SLAVE_SCSR_R (*((volatile unsigned long *)0x40020804))
-#define I2C0_SLAVE_SDR_R (*((volatile unsigned long *)0x40020808))
-#define I2C0_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002080C))
-#define I2C0_SLAVE_SRIS_R (*((volatile unsigned long *)0x40020810))
-#define I2C0_SLAVE_SMIS_R (*((volatile unsigned long *)0x40020814))
-#define I2C0_SLAVE_SICR_R (*((volatile unsigned long *)0x40020818))
-#define I2C0_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002081C))
-#define I2C0_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40020820))
-
-//*****************************************************************************
-//
-// I2C registers (I2C1 MASTER)
-//
-//*****************************************************************************
-#define I2C1_MASTER_MSA_R (*((volatile unsigned long *)0x40021000))
-#define I2C1_MASTER_MCS_R (*((volatile unsigned long *)0x40021004))
-#define I2C1_MASTER_MDR_R (*((volatile unsigned long *)0x40021008))
-#define I2C1_MASTER_MTPR_R (*((volatile unsigned long *)0x4002100C))
-#define I2C1_MASTER_MIMR_R (*((volatile unsigned long *)0x40021010))
-#define I2C1_MASTER_MRIS_R (*((volatile unsigned long *)0x40021014))
-#define I2C1_MASTER_MMIS_R (*((volatile unsigned long *)0x40021018))
-#define I2C1_MASTER_MICR_R (*((volatile unsigned long *)0x4002101C))
-#define I2C1_MASTER_MCR_R (*((volatile unsigned long *)0x40021020))
-#define I2C1_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40021024))
-#define I2C1_MASTER_MBMON_R (*((volatile unsigned long *)0x4002102C))
-
-//*****************************************************************************
-//
-// I2C registers (I2C1 SLAVE)
-//
-//*****************************************************************************
-#define I2C1_SLAVE_SOAR_R (*((volatile unsigned long *)0x40021800))
-#define I2C1_SLAVE_SCSR_R (*((volatile unsigned long *)0x40021804))
-#define I2C1_SLAVE_SDR_R (*((volatile unsigned long *)0x40021808))
-#define I2C1_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002180C))
-#define I2C1_SLAVE_SRIS_R (*((volatile unsigned long *)0x40021810))
-#define I2C1_SLAVE_SMIS_R (*((volatile unsigned long *)0x40021814))
-#define I2C1_SLAVE_SICR_R (*((volatile unsigned long *)0x40021818))
-#define I2C1_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002181C))
-#define I2C1_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40021820))
-
-//*****************************************************************************
-//
-// I2C registers (I2C2 MASTER)
-//
-//*****************************************************************************
-#define I2C2_MASTER_MSA_R (*((volatile unsigned long *)0x40022000))
-#define I2C2_MASTER_MCS_R (*((volatile unsigned long *)0x40022004))
-#define I2C2_MASTER_MDR_R (*((volatile unsigned long *)0x40022008))
-#define I2C2_MASTER_MTPR_R (*((volatile unsigned long *)0x4002200C))
-#define I2C2_MASTER_MIMR_R (*((volatile unsigned long *)0x40022010))
-#define I2C2_MASTER_MRIS_R (*((volatile unsigned long *)0x40022014))
-#define I2C2_MASTER_MMIS_R (*((volatile unsigned long *)0x40022018))
-#define I2C2_MASTER_MICR_R (*((volatile unsigned long *)0x4002201C))
-#define I2C2_MASTER_MCR_R (*((volatile unsigned long *)0x40022020))
-#define I2C2_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40022024))
-#define I2C2_MASTER_MBMON_R (*((volatile unsigned long *)0x4002202C))
-
-//*****************************************************************************
-//
-// I2C registers (I2C2 SLAVE)
-//
-//*****************************************************************************
-#define I2C2_SLAVE_SOAR_R (*((volatile unsigned long *)0x40022800))
-#define I2C2_SLAVE_SCSR_R (*((volatile unsigned long *)0x40022804))
-#define I2C2_SLAVE_SDR_R (*((volatile unsigned long *)0x40022808))
-#define I2C2_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002280C))
-#define I2C2_SLAVE_SRIS_R (*((volatile unsigned long *)0x40022810))
-#define I2C2_SLAVE_SMIS_R (*((volatile unsigned long *)0x40022814))
-#define I2C2_SLAVE_SICR_R (*((volatile unsigned long *)0x40022818))
-#define I2C2_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002281C))
-#define I2C2_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40022820))
-
-//*****************************************************************************
-//
-// I2C registers (I2C3 MASTER)
-//
-//*****************************************************************************
-#define I2C3_MASTER_MSA_R (*((volatile unsigned long *)0x40023000))
-#define I2C3_MASTER_MCS_R (*((volatile unsigned long *)0x40023004))
-#define I2C3_MASTER_MDR_R (*((volatile unsigned long *)0x40023008))
-#define I2C3_MASTER_MTPR_R (*((volatile unsigned long *)0x4002300C))
-#define I2C3_MASTER_MIMR_R (*((volatile unsigned long *)0x40023010))
-#define I2C3_MASTER_MRIS_R (*((volatile unsigned long *)0x40023014))
-#define I2C3_MASTER_MMIS_R (*((volatile unsigned long *)0x40023018))
-#define I2C3_MASTER_MICR_R (*((volatile unsigned long *)0x4002301C))
-#define I2C3_MASTER_MCR_R (*((volatile unsigned long *)0x40023020))
-#define I2C3_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40023024))
-#define I2C3_MASTER_MBMON_R (*((volatile unsigned long *)0x4002302C))
-
-//*****************************************************************************
-//
-// I2C registers (I2C3 SLAVE)
-//
-//*****************************************************************************
-#define I2C3_SLAVE_SOAR_R (*((volatile unsigned long *)0x40023800))
-#define I2C3_SLAVE_SCSR_R (*((volatile unsigned long *)0x40023804))
-#define I2C3_SLAVE_SDR_R (*((volatile unsigned long *)0x40023808))
-#define I2C3_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002380C))
-#define I2C3_SLAVE_SRIS_R (*((volatile unsigned long *)0x40023810))
-#define I2C3_SLAVE_SMIS_R (*((volatile unsigned long *)0x40023814))
-#define I2C3_SLAVE_SICR_R (*((volatile unsigned long *)0x40023818))
-#define I2C3_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002381C))
-#define I2C3_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40023820))
-
-//*****************************************************************************
-//
-// GPIO registers (PORTE)
-//
-//*****************************************************************************
-#define GPIO_PORTE_DATA_BITS_R ((volatile unsigned long *)0x40024000)
-#define GPIO_PORTE_DATA_R (*((volatile unsigned long *)0x400243FC))
-#define GPIO_PORTE_DIR_R (*((volatile unsigned long *)0x40024400))
-#define GPIO_PORTE_IS_R (*((volatile unsigned long *)0x40024404))
-#define GPIO_PORTE_IBE_R (*((volatile unsigned long *)0x40024408))
-#define GPIO_PORTE_IEV_R (*((volatile unsigned long *)0x4002440C))
-#define GPIO_PORTE_IM_R (*((volatile unsigned long *)0x40024410))
-#define GPIO_PORTE_RIS_R (*((volatile unsigned long *)0x40024414))
-#define GPIO_PORTE_MIS_R (*((volatile unsigned long *)0x40024418))
-#define GPIO_PORTE_ICR_R (*((volatile unsigned long *)0x4002441C))
-#define GPIO_PORTE_AFSEL_R (*((volatile unsigned long *)0x40024420))
-#define GPIO_PORTE_DR2R_R (*((volatile unsigned long *)0x40024500))
-#define GPIO_PORTE_DR4R_R (*((volatile unsigned long *)0x40024504))
-#define GPIO_PORTE_DR8R_R (*((volatile unsigned long *)0x40024508))
-#define GPIO_PORTE_ODR_R (*((volatile unsigned long *)0x4002450C))
-#define GPIO_PORTE_PUR_R (*((volatile unsigned long *)0x40024510))
-#define GPIO_PORTE_PDR_R (*((volatile unsigned long *)0x40024514))
-#define GPIO_PORTE_SLR_R (*((volatile unsigned long *)0x40024518))
-#define GPIO_PORTE_DEN_R (*((volatile unsigned long *)0x4002451C))
-#define GPIO_PORTE_LOCK_R (*((volatile unsigned long *)0x40024520))
-#define GPIO_PORTE_CR_R (*((volatile unsigned long *)0x40024524))
-#define GPIO_PORTE_AMSEL_R (*((volatile unsigned long *)0x40024528))
-#define GPIO_PORTE_PCTL_R (*((volatile unsigned long *)0x4002452C))
-#define GPIO_PORTE_ADCCTL_R (*((volatile unsigned long *)0x40024530))
-#define GPIO_PORTE_DMACTL_R (*((volatile unsigned long *)0x40024534))
-#define GPIO_PORTE_SI_R (*((volatile unsigned long *)0x40024538))
-
-//*****************************************************************************
-//
-// GPIO registers (PORTF)
-//
-//*****************************************************************************
-#define GPIO_PORTF_DATA_BITS_R ((volatile unsigned long *)0x40025000)
-#define GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC))
-#define GPIO_PORTF_DIR_R (*((volatile unsigned long *)0x40025400))
-#define GPIO_PORTF_IS_R (*((volatile unsigned long *)0x40025404))
-#define GPIO_PORTF_IBE_R (*((volatile unsigned long *)0x40025408))
-#define GPIO_PORTF_IEV_R (*((volatile unsigned long *)0x4002540C))
-#define GPIO_PORTF_IM_R (*((volatile unsigned long *)0x40025410))
-#define GPIO_PORTF_RIS_R (*((volatile unsigned long *)0x40025414))
-#define GPIO_PORTF_MIS_R (*((volatile unsigned long *)0x40025418))
-#define GPIO_PORTF_ICR_R (*((volatile unsigned long *)0x4002541C))
-#define GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420))
-#define GPIO_PORTF_DR2R_R (*((volatile unsigned long *)0x40025500))
-#define GPIO_PORTF_DR4R_R (*((volatile unsigned long *)0x40025504))
-#define GPIO_PORTF_DR8R_R (*((volatile unsigned long *)0x40025508))
-#define GPIO_PORTF_ODR_R (*((volatile unsigned long *)0x4002550C))
-#define GPIO_PORTF_PUR_R (*((volatile unsigned long *)0x40025510))
-#define GPIO_PORTF_PDR_R (*((volatile unsigned long *)0x40025514))
-#define GPIO_PORTF_SLR_R (*((volatile unsigned long *)0x40025518))
-#define GPIO_PORTF_DEN_R (*((volatile unsigned long *)0x4002551C))
-#define GPIO_PORTF_LOCK_R (*((volatile unsigned long *)0x40025520))
-#define GPIO_PORTF_CR_R (*((volatile unsigned long *)0x40025524))
-#define GPIO_PORTF_AMSEL_R (*((volatile unsigned long *)0x40025528))
-#define GPIO_PORTF_PCTL_R (*((volatile unsigned long *)0x4002552C))
-#define GPIO_PORTF_ADCCTL_R (*((volatile unsigned long *)0x40025530))
-#define GPIO_PORTF_DMACTL_R (*((volatile unsigned long *)0x40025534))
-#define GPIO_PORTF_SI_R (*((volatile unsigned long *)0x40025538))
-
-//*****************************************************************************
-//
-// Timer registers (TIMER0)
-//
-//*****************************************************************************
-#define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000))
-#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004))
-#define TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008))
-#define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C))
-#define TIMER0_SYNC_R (*((volatile unsigned long *)0x40030010))
-#define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018))
-#define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C))
-#define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020))
-#define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024))
-#define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028))
-#define TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C))
-#define TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030))
-#define TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034))
-#define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038))
-#define TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C))
-#define TIMER0_TAPMR_R (*((volatile unsigned long *)0x40030040))
-#define TIMER0_TBPMR_R (*((volatile unsigned long *)0x40030044))
-#define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048))
-#define TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C))
-#define TIMER0_TAV_R (*((volatile unsigned long *)0x40030050))
-#define TIMER0_TBV_R (*((volatile unsigned long *)0x40030054))
-#define TIMER0_RTCPD_R (*((volatile unsigned long *)0x40030058))
-#define TIMER0_TAPS_R (*((volatile unsigned long *)0x4003005C))
-#define TIMER0_TBPS_R (*((volatile unsigned long *)0x40030060))
-#define TIMER0_TAPV_R (*((volatile unsigned long *)0x40030064))
-#define TIMER0_TBPV_R (*((volatile unsigned long *)0x40030068))
-#define TIMER0_PP_R (*((volatile unsigned long *)0x40030FC0))
-
-//*****************************************************************************
-//
-// Timer registers (TIMER1)
-//
-//*****************************************************************************
-#define TIMER1_CFG_R (*((volatile unsigned long *)0x40031000))
-#define TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004))
-#define TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008))
-#define TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C))
-#define TIMER1_SYNC_R (*((volatile unsigned long *)0x40031010))
-#define TIMER1_IMR_R (*((volatile unsigned long *)0x40031018))
-#define TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C))
-#define TIMER1_MIS_R (*((volatile unsigned long *)0x40031020))
-#define TIMER1_ICR_R (*((volatile unsigned long *)0x40031024))
-#define TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028))
-#define TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C))
-#define TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030))
-#define TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034))
-#define TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038))
-#define TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C))
-#define TIMER1_TAPMR_R (*((volatile unsigned long *)0x40031040))
-#define TIMER1_TBPMR_R (*((volatile unsigned long *)0x40031044))
-#define TIMER1_TAR_R (*((volatile unsigned long *)0x40031048))
-#define TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C))
-#define TIMER1_TAV_R (*((volatile unsigned long *)0x40031050))
-#define TIMER1_TBV_R (*((volatile unsigned long *)0x40031054))
-#define TIMER1_RTCPD_R (*((volatile unsigned long *)0x40031058))
-#define TIMER1_TAPS_R (*((volatile unsigned long *)0x4003105C))
-#define TIMER1_TBPS_R (*((volatile unsigned long *)0x40031060))
-#define TIMER1_TAPV_R (*((volatile unsigned long *)0x40031064))
-#define TIMER1_TBPV_R (*((volatile unsigned long *)0x40031068))
-#define TIMER1_PP_R (*((volatile unsigned long *)0x40031FC0))
-
-//*****************************************************************************
-//
-// Timer registers (TIMER2)
-//
-//*****************************************************************************
-#define TIMER2_CFG_R (*((volatile unsigned long *)0x40032000))
-#define TIMER2_TAMR_R (*((volatile unsigned long *)0x40032004))
-#define TIMER2_TBMR_R (*((volatile unsigned long *)0x40032008))
-#define TIMER2_CTL_R (*((volatile unsigned long *)0x4003200C))
-#define TIMER2_SYNC_R (*((volatile unsigned long *)0x40032010))
-#define TIMER2_IMR_R (*((volatile unsigned long *)0x40032018))
-#define TIMER2_RIS_R (*((volatile unsigned long *)0x4003201C))
-#define TIMER2_MIS_R (*((volatile unsigned long *)0x40032020))
-#define TIMER2_ICR_R (*((volatile unsigned long *)0x40032024))
-#define TIMER2_TAILR_R (*((volatile unsigned long *)0x40032028))
-#define TIMER2_TBILR_R (*((volatile unsigned long *)0x4003202C))
-#define TIMER2_TAMATCHR_R (*((volatile unsigned long *)0x40032030))
-#define TIMER2_TBMATCHR_R (*((volatile unsigned long *)0x40032034))
-#define TIMER2_TAPR_R (*((volatile unsigned long *)0x40032038))
-#define TIMER2_TBPR_R (*((volatile unsigned long *)0x4003203C))
-#define TIMER2_TAPMR_R (*((volatile unsigned long *)0x40032040))
-#define TIMER2_TBPMR_R (*((volatile unsigned long *)0x40032044))
-#define TIMER2_TAR_R (*((volatile unsigned long *)0x40032048))
-#define TIMER2_TBR_R (*((volatile unsigned long *)0x4003204C))
-#define TIMER2_TAV_R (*((volatile unsigned long *)0x40032050))
-#define TIMER2_TBV_R (*((volatile unsigned long *)0x40032054))
-#define TIMER2_RTCPD_R (*((volatile unsigned long *)0x40032058))
-#define TIMER2_TAPS_R (*((volatile unsigned long *)0x4003205C))
-#define TIMER2_TBPS_R (*((volatile unsigned long *)0x40032060))
-#define TIMER2_TAPV_R (*((volatile unsigned long *)0x40032064))
-#define TIMER2_TBPV_R (*((volatile unsigned long *)0x40032068))
-#define TIMER2_PP_R (*((volatile unsigned long *)0x40032FC0))
-
-//*****************************************************************************
-//
-// Timer registers (TIMER3)
-//
-//*****************************************************************************
-#define TIMER3_CFG_R (*((volatile unsigned long *)0x40033000))
-#define TIMER3_TAMR_R (*((volatile unsigned long *)0x40033004))
-#define TIMER3_TBMR_R (*((volatile unsigned long *)0x40033008))
-#define TIMER3_CTL_R (*((volatile unsigned long *)0x4003300C))
-#define TIMER3_SYNC_R (*((volatile unsigned long *)0x40033010))
-#define TIMER3_IMR_R (*((volatile unsigned long *)0x40033018))
-#define TIMER3_RIS_R (*((volatile unsigned long *)0x4003301C))
-#define TIMER3_MIS_R (*((volatile unsigned long *)0x40033020))
-#define TIMER3_ICR_R (*((volatile unsigned long *)0x40033024))
-#define TIMER3_TAILR_R (*((volatile unsigned long *)0x40033028))
-#define TIMER3_TBILR_R (*((volatile unsigned long *)0x4003302C))
-#define TIMER3_TAMATCHR_R (*((volatile unsigned long *)0x40033030))
-#define TIMER3_TBMATCHR_R (*((volatile unsigned long *)0x40033034))
-#define TIMER3_TAPR_R (*((volatile unsigned long *)0x40033038))
-#define TIMER3_TBPR_R (*((volatile unsigned long *)0x4003303C))
-#define TIMER3_TAPMR_R (*((volatile unsigned long *)0x40033040))
-#define TIMER3_TBPMR_R (*((volatile unsigned long *)0x40033044))
-#define TIMER3_TAR_R (*((volatile unsigned long *)0x40033048))
-#define TIMER3_TBR_R (*((volatile unsigned long *)0x4003304C))
-#define TIMER3_TAV_R (*((volatile unsigned long *)0x40033050))
-#define TIMER3_TBV_R (*((volatile unsigned long *)0x40033054))
-#define TIMER3_RTCPD_R (*((volatile unsigned long *)0x40033058))
-#define TIMER3_TAPS_R (*((volatile unsigned long *)0x4003305C))
-#define TIMER3_TBPS_R (*((volatile unsigned long *)0x40033060))
-#define TIMER3_TAPV_R (*((volatile unsigned long *)0x40033064))
-#define TIMER3_TBPV_R (*((volatile unsigned long *)0x40033068))
-#define TIMER3_PP_R (*((volatile unsigned long *)0x40033FC0))
-
-//*****************************************************************************
-//
-// Timer registers (TIMER4)
-//
-//*****************************************************************************
-#define TIMER4_CFG_R (*((volatile unsigned long *)0x40034000))
-#define TIMER4_TAMR_R (*((volatile unsigned long *)0x40034004))
-#define TIMER4_TBMR_R (*((volatile unsigned long *)0x40034008))
-#define TIMER4_CTL_R (*((volatile unsigned long *)0x4003400C))
-#define TIMER4_SYNC_R (*((volatile unsigned long *)0x40034010))
-#define TIMER4_IMR_R (*((volatile unsigned long *)0x40034018))
-#define TIMER4_RIS_R (*((volatile unsigned long *)0x4003401C))
-#define TIMER4_MIS_R (*((volatile unsigned long *)0x40034020))
-#define TIMER4_ICR_R (*((volatile unsigned long *)0x40034024))
-#define TIMER4_TAILR_R (*((volatile unsigned long *)0x40034028))
-#define TIMER4_TBILR_R (*((volatile unsigned long *)0x4003402C))
-#define TIMER4_TAMATCHR_R (*((volatile unsigned long *)0x40034030))
-#define TIMER4_TBMATCHR_R (*((volatile unsigned long *)0x40034034))
-#define TIMER4_TAPR_R (*((volatile unsigned long *)0x40034038))
-#define TIMER4_TBPR_R (*((volatile unsigned long *)0x4003403C))
-#define TIMER4_TAPMR_R (*((volatile unsigned long *)0x40034040))
-#define TIMER4_TBPMR_R (*((volatile unsigned long *)0x40034044))
-#define TIMER4_TAR_R (*((volatile unsigned long *)0x40034048))
-#define TIMER4_TBR_R (*((volatile unsigned long *)0x4003404C))
-#define TIMER4_TAV_R (*((volatile unsigned long *)0x40034050))
-#define TIMER4_TBV_R (*((volatile unsigned long *)0x40034054))
-#define TIMER4_RTCPD_R (*((volatile unsigned long *)0x40034058))
-#define TIMER4_TAPS_R (*((volatile unsigned long *)0x4003405C))
-#define TIMER4_TBPS_R (*((volatile unsigned long *)0x40034060))
-#define TIMER4_TAPV_R (*((volatile unsigned long *)0x40034064))
-#define TIMER4_TBPV_R (*((volatile unsigned long *)0x40034068))
-#define TIMER4_PP_R (*((volatile unsigned long *)0x40034FC0))
-
-//*****************************************************************************
-//
-// Timer registers (TIMER5)
-//
-//*****************************************************************************
-#define TIMER5_CFG_R (*((volatile unsigned long *)0x40035000))
-#define TIMER5_TAMR_R (*((volatile unsigned long *)0x40035004))
-#define TIMER5_TBMR_R (*((volatile unsigned long *)0x40035008))
-#define TIMER5_CTL_R (*((volatile unsigned long *)0x4003500C))
-#define TIMER5_SYNC_R (*((volatile unsigned long *)0x40035010))
-#define TIMER5_IMR_R (*((volatile unsigned long *)0x40035018))
-#define TIMER5_RIS_R (*((volatile unsigned long *)0x4003501C))
-#define TIMER5_MIS_R (*((volatile unsigned long *)0x40035020))
-#define TIMER5_ICR_R (*((volatile unsigned long *)0x40035024))
-#define TIMER5_TAILR_R (*((volatile unsigned long *)0x40035028))
-#define TIMER5_TBILR_R (*((volatile unsigned long *)0x4003502C))
-#define TIMER5_TAMATCHR_R (*((volatile unsigned long *)0x40035030))
-#define TIMER5_TBMATCHR_R (*((volatile unsigned long *)0x40035034))
-#define TIMER5_TAPR_R (*((volatile unsigned long *)0x40035038))
-#define TIMER5_TBPR_R (*((volatile unsigned long *)0x4003503C))
-#define TIMER5_TAPMR_R (*((volatile unsigned long *)0x40035040))
-#define TIMER5_TBPMR_R (*((volatile unsigned long *)0x40035044))
-#define TIMER5_TAR_R (*((volatile unsigned long *)0x40035048))
-#define TIMER5_TBR_R (*((volatile unsigned long *)0x4003504C))
-#define TIMER5_TAV_R (*((volatile unsigned long *)0x40035050))
-#define TIMER5_TBV_R (*((volatile unsigned long *)0x40035054))
-#define TIMER5_RTCPD_R (*((volatile unsigned long *)0x40035058))
-#define TIMER5_TAPS_R (*((volatile unsigned long *)0x4003505C))
-#define TIMER5_TBPS_R (*((volatile unsigned long *)0x40035060))
-#define TIMER5_TAPV_R (*((volatile unsigned long *)0x40035064))
-#define TIMER5_TBPV_R (*((volatile unsigned long *)0x40035068))
-#define TIMER5_PP_R (*((volatile unsigned long *)0x40035FC0))
-
-//*****************************************************************************
-//
-// Timer registers (WTIMER0)
-//
-//*****************************************************************************
-#define WTIMER0_CFG_R (*((volatile unsigned long *)0x40036000))
-#define WTIMER0_TAMR_R (*((volatile unsigned long *)0x40036004))
-#define WTIMER0_TBMR_R (*((volatile unsigned long *)0x40036008))
-#define WTIMER0_CTL_R (*((volatile unsigned long *)0x4003600C))
-#define WTIMER0_SYNC_R (*((volatile unsigned long *)0x40036010))
-#define WTIMER0_IMR_R (*((volatile unsigned long *)0x40036018))
-#define WTIMER0_RIS_R (*((volatile unsigned long *)0x4003601C))
-#define WTIMER0_MIS_R (*((volatile unsigned long *)0x40036020))
-#define WTIMER0_ICR_R (*((volatile unsigned long *)0x40036024))
-#define WTIMER0_TAILR_R (*((volatile unsigned long *)0x40036028))
-#define WTIMER0_TBILR_R (*((volatile unsigned long *)0x4003602C))
-#define WTIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40036030))
-#define WTIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40036034))
-#define WTIMER0_TAPR_R (*((volatile unsigned long *)0x40036038))
-#define WTIMER0_TBPR_R (*((volatile unsigned long *)0x4003603C))
-#define WTIMER0_TAPMR_R (*((volatile unsigned long *)0x40036040))
-#define WTIMER0_TBPMR_R (*((volatile unsigned long *)0x40036044))
-#define WTIMER0_TAR_R (*((volatile unsigned long *)0x40036048))
-#define WTIMER0_TBR_R (*((volatile unsigned long *)0x4003604C))
-#define WTIMER0_TAV_R (*((volatile unsigned long *)0x40036050))
-#define WTIMER0_TBV_R (*((volatile unsigned long *)0x40036054))
-#define WTIMER0_RTCPD_R (*((volatile unsigned long *)0x40036058))
-#define WTIMER0_TAPS_R (*((volatile unsigned long *)0x4003605C))
-#define WTIMER0_TBPS_R (*((volatile unsigned long *)0x40036060))
-#define WTIMER0_TAPV_R (*((volatile unsigned long *)0x40036064))
-#define WTIMER0_TBPV_R (*((volatile unsigned long *)0x40036068))
-#define WTIMER0_PP_R (*((volatile unsigned long *)0x40036FC0))
-
-//*****************************************************************************
-//
-// Timer registers (WTIMER1)
-//
-//*****************************************************************************
-#define WTIMER1_CFG_R (*((volatile unsigned long *)0x40037000))
-#define WTIMER1_TAMR_R (*((volatile unsigned long *)0x40037004))
-#define WTIMER1_TBMR_R (*((volatile unsigned long *)0x40037008))
-#define WTIMER1_CTL_R (*((volatile unsigned long *)0x4003700C))
-#define WTIMER1_SYNC_R (*((volatile unsigned long *)0x40037010))
-#define WTIMER1_IMR_R (*((volatile unsigned long *)0x40037018))
-#define WTIMER1_RIS_R (*((volatile unsigned long *)0x4003701C))
-#define WTIMER1_MIS_R (*((volatile unsigned long *)0x40037020))
-#define WTIMER1_ICR_R (*((volatile unsigned long *)0x40037024))
-#define WTIMER1_TAILR_R (*((volatile unsigned long *)0x40037028))
-#define WTIMER1_TBILR_R (*((volatile unsigned long *)0x4003702C))
-#define WTIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40037030))
-#define WTIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40037034))
-#define WTIMER1_TAPR_R (*((volatile unsigned long *)0x40037038))
-#define WTIMER1_TBPR_R (*((volatile unsigned long *)0x4003703C))
-#define WTIMER1_TAPMR_R (*((volatile unsigned long *)0x40037040))
-#define WTIMER1_TBPMR_R (*((volatile unsigned long *)0x40037044))
-#define WTIMER1_TAR_R (*((volatile unsigned long *)0x40037048))
-#define WTIMER1_TBR_R (*((volatile unsigned long *)0x4003704C))
-#define WTIMER1_TAV_R (*((volatile unsigned long *)0x40037050))
-#define WTIMER1_TBV_R (*((volatile unsigned long *)0x40037054))
-#define WTIMER1_RTCPD_R (*((volatile unsigned long *)0x40037058))
-#define WTIMER1_TAPS_R (*((volatile unsigned long *)0x4003705C))
-#define WTIMER1_TBPS_R (*((volatile unsigned long *)0x40037060))
-#define WTIMER1_TAPV_R (*((volatile unsigned long *)0x40037064))
-#define WTIMER1_TBPV_R (*((volatile unsigned long *)0x40037068))
-#define WTIMER1_PP_R (*((volatile unsigned long *)0x40037FC0))
-
-//*****************************************************************************
-//
-// ADC registers (ADC0)
-//
-//*****************************************************************************
-#define ADC0_ACTSS_R (*((volatile unsigned long *)0x40038000))
-#define ADC0_RIS_R (*((volatile unsigned long *)0x40038004))
-#define ADC0_IM_R (*((volatile unsigned long *)0x40038008))
-#define ADC0_ISC_R (*((volatile unsigned long *)0x4003800C))
-#define ADC0_OSTAT_R (*((volatile unsigned long *)0x40038010))
-#define ADC0_EMUX_R (*((volatile unsigned long *)0x40038014))
-#define ADC0_USTAT_R (*((volatile unsigned long *)0x40038018))
-#define ADC0_SSPRI_R (*((volatile unsigned long *)0x40038020))
-#define ADC0_SPC_R (*((volatile unsigned long *)0x40038024))
-#define ADC0_PSSI_R (*((volatile unsigned long *)0x40038028))
-#define ADC0_SAC_R (*((volatile unsigned long *)0x40038030))
-#define ADC0_DCISC_R (*((volatile unsigned long *)0x40038034))
-#define ADC0_SSMUX0_R (*((volatile unsigned long *)0x40038040))
-#define ADC0_SSCTL0_R (*((volatile unsigned long *)0x40038044))
-#define ADC0_SSFIFO0_R (*((volatile unsigned long *)0x40038048))
-#define ADC0_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C))
-#define ADC0_SSOP0_R (*((volatile unsigned long *)0x40038050))
-#define ADC0_SSDC0_R (*((volatile unsigned long *)0x40038054))
-#define ADC0_SSMUX1_R (*((volatile unsigned long *)0x40038060))
-#define ADC0_SSCTL1_R (*((volatile unsigned long *)0x40038064))
-#define ADC0_SSFIFO1_R (*((volatile unsigned long *)0x40038068))
-#define ADC0_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C))
-#define ADC0_SSOP1_R (*((volatile unsigned long *)0x40038070))
-#define ADC0_SSDC1_R (*((volatile unsigned long *)0x40038074))
-#define ADC0_SSMUX2_R (*((volatile unsigned long *)0x40038080))
-#define ADC0_SSCTL2_R (*((volatile unsigned long *)0x40038084))
-#define ADC0_SSFIFO2_R (*((volatile unsigned long *)0x40038088))
-#define ADC0_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C))
-#define ADC0_SSOP2_R (*((volatile unsigned long *)0x40038090))
-#define ADC0_SSDC2_R (*((volatile unsigned long *)0x40038094))
-#define ADC0_SSMUX3_R (*((volatile unsigned long *)0x400380A0))
-#define ADC0_SSCTL3_R (*((volatile unsigned long *)0x400380A4))
-#define ADC0_SSFIFO3_R (*((volatile unsigned long *)0x400380A8))
-#define ADC0_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC))
-#define ADC0_SSOP3_R (*((volatile unsigned long *)0x400380B0))
-#define ADC0_SSDC3_R (*((volatile unsigned long *)0x400380B4))
-#define ADC0_DCRIC_R (*((volatile unsigned long *)0x40038D00))
-#define ADC0_DCCTL0_R (*((volatile unsigned long *)0x40038E00))
-#define ADC0_DCCTL1_R (*((volatile unsigned long *)0x40038E04))
-#define ADC0_DCCTL2_R (*((volatile unsigned long *)0x40038E08))
-#define ADC0_DCCTL3_R (*((volatile unsigned long *)0x40038E0C))
-#define ADC0_DCCTL4_R (*((volatile unsigned long *)0x40038E10))
-#define ADC0_DCCTL5_R (*((volatile unsigned long *)0x40038E14))
-#define ADC0_DCCTL6_R (*((volatile unsigned long *)0x40038E18))
-#define ADC0_DCCTL7_R (*((volatile unsigned long *)0x40038E1C))
-#define ADC0_DCCMP0_R (*((volatile unsigned long *)0x40038E40))
-#define ADC0_DCCMP1_R (*((volatile unsigned long *)0x40038E44))
-#define ADC0_DCCMP2_R (*((volatile unsigned long *)0x40038E48))
-#define ADC0_DCCMP3_R (*((volatile unsigned long *)0x40038E4C))
-#define ADC0_DCCMP4_R (*((volatile unsigned long *)0x40038E50))
-#define ADC0_DCCMP5_R (*((volatile unsigned long *)0x40038E54))
-#define ADC0_DCCMP6_R (*((volatile unsigned long *)0x40038E58))
-#define ADC0_DCCMP7_R (*((volatile unsigned long *)0x40038E5C))
-#define ADC0_PP_R (*((volatile unsigned long *)0x40038FC0))
-#define ADC0_PC_R (*((volatile unsigned long *)0x40038FC4))
-#define ADC0_CC_R (*((volatile unsigned long *)0x40038FC8))
-
-//*****************************************************************************
-//
-// ADC registers (ADC1)
-//
-//*****************************************************************************
-#define ADC1_ACTSS_R (*((volatile unsigned long *)0x40039000))
-#define ADC1_RIS_R (*((volatile unsigned long *)0x40039004))
-#define ADC1_IM_R (*((volatile unsigned long *)0x40039008))
-#define ADC1_ISC_R (*((volatile unsigned long *)0x4003900C))
-#define ADC1_OSTAT_R (*((volatile unsigned long *)0x40039010))
-#define ADC1_EMUX_R (*((volatile unsigned long *)0x40039014))
-#define ADC1_USTAT_R (*((volatile unsigned long *)0x40039018))
-#define ADC1_SSPRI_R (*((volatile unsigned long *)0x40039020))
-#define ADC1_SPC_R (*((volatile unsigned long *)0x40039024))
-#define ADC1_PSSI_R (*((volatile unsigned long *)0x40039028))
-#define ADC1_SAC_R (*((volatile unsigned long *)0x40039030))
-#define ADC1_DCISC_R (*((volatile unsigned long *)0x40039034))
-#define ADC1_SSMUX0_R (*((volatile unsigned long *)0x40039040))
-#define ADC1_SSCTL0_R (*((volatile unsigned long *)0x40039044))
-#define ADC1_SSFIFO0_R (*((volatile unsigned long *)0x40039048))
-#define ADC1_SSFSTAT0_R (*((volatile unsigned long *)0x4003904C))
-#define ADC1_SSOP0_R (*((volatile unsigned long *)0x40039050))
-#define ADC1_SSDC0_R (*((volatile unsigned long *)0x40039054))
-#define ADC1_SSMUX1_R (*((volatile unsigned long *)0x40039060))
-#define ADC1_SSCTL1_R (*((volatile unsigned long *)0x40039064))
-#define ADC1_SSFIFO1_R (*((volatile unsigned long *)0x40039068))
-#define ADC1_SSFSTAT1_R (*((volatile unsigned long *)0x4003906C))
-#define ADC1_SSOP1_R (*((volatile unsigned long *)0x40039070))
-#define ADC1_SSDC1_R (*((volatile unsigned long *)0x40039074))
-#define ADC1_SSMUX2_R (*((volatile unsigned long *)0x40039080))
-#define ADC1_SSCTL2_R (*((volatile unsigned long *)0x40039084))
-#define ADC1_SSFIFO2_R (*((volatile unsigned long *)0x40039088))
-#define ADC1_SSFSTAT2_R (*((volatile unsigned long *)0x4003908C))
-#define ADC1_SSOP2_R (*((volatile unsigned long *)0x40039090))
-#define ADC1_SSDC2_R (*((volatile unsigned long *)0x40039094))
-#define ADC1_SSMUX3_R (*((volatile unsigned long *)0x400390A0))
-#define ADC1_SSCTL3_R (*((volatile unsigned long *)0x400390A4))
-#define ADC1_SSFIFO3_R (*((volatile unsigned long *)0x400390A8))
-#define ADC1_SSFSTAT3_R (*((volatile unsigned long *)0x400390AC))
-#define ADC1_SSOP3_R (*((volatile unsigned long *)0x400390B0))
-#define ADC1_SSDC3_R (*((volatile unsigned long *)0x400390B4))
-#define ADC1_DCRIC_R (*((volatile unsigned long *)0x40039D00))
-#define ADC1_DCCTL0_R (*((volatile unsigned long *)0x40039E00))
-#define ADC1_DCCTL1_R (*((volatile unsigned long *)0x40039E04))
-#define ADC1_DCCTL2_R (*((volatile unsigned long *)0x40039E08))
-#define ADC1_DCCTL3_R (*((volatile unsigned long *)0x40039E0C))
-#define ADC1_DCCTL4_R (*((volatile unsigned long *)0x40039E10))
-#define ADC1_DCCTL5_R (*((volatile unsigned long *)0x40039E14))
-#define ADC1_DCCTL6_R (*((volatile unsigned long *)0x40039E18))
-#define ADC1_DCCTL7_R (*((volatile unsigned long *)0x40039E1C))
-#define ADC1_DCCMP0_R (*((volatile unsigned long *)0x40039E40))
-#define ADC1_DCCMP1_R (*((volatile unsigned long *)0x40039E44))
-#define ADC1_DCCMP2_R (*((volatile unsigned long *)0x40039E48))
-#define ADC1_DCCMP3_R (*((volatile unsigned long *)0x40039E4C))
-#define ADC1_DCCMP4_R (*((volatile unsigned long *)0x40039E50))
-#define ADC1_DCCMP5_R (*((volatile unsigned long *)0x40039E54))
-#define ADC1_DCCMP6_R (*((volatile unsigned long *)0x40039E58))
-#define ADC1_DCCMP7_R (*((volatile unsigned long *)0x40039E5C))
-#define ADC1_PP_R (*((volatile unsigned long *)0x40039FC0))
-#define ADC1_PC_R (*((volatile unsigned long *)0x40039FC4))
-#define ADC1_CC_R (*((volatile unsigned long *)0x40039FC8))
-
-//*****************************************************************************
-//
-// Comparator registers (COMP)
-//
-//*****************************************************************************
-#define COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000))
-#define COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004))
-#define COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008))
-#define COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010))
-#define COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020))
-#define COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024))
-#define COMP_ACSTAT1_R (*((volatile unsigned long *)0x4003C040))
-#define COMP_ACCTL1_R (*((volatile unsigned long *)0x4003C044))
-#define COMP_PP_R (*((volatile unsigned long *)0x4003CFC0))
-
-//*****************************************************************************
-//
-// CAN registers (CAN0)
-//
-//*****************************************************************************
-#define CAN0_CTL_R (*((volatile unsigned long *)0x40040000))
-#define CAN0_STS_R (*((volatile unsigned long *)0x40040004))
-#define CAN0_ERR_R (*((volatile unsigned long *)0x40040008))
-#define CAN0_BIT_R (*((volatile unsigned long *)0x4004000C))
-#define CAN0_INT_R (*((volatile unsigned long *)0x40040010))
-#define CAN0_TST_R (*((volatile unsigned long *)0x40040014))
-#define CAN0_BRPE_R (*((volatile unsigned long *)0x40040018))
-#define CAN0_IF1CRQ_R (*((volatile unsigned long *)0x40040020))
-#define CAN0_IF1CMSK_R (*((volatile unsigned long *)0x40040024))
-#define CAN0_IF1MSK1_R (*((volatile unsigned long *)0x40040028))
-#define CAN0_IF1MSK2_R (*((volatile unsigned long *)0x4004002C))
-#define CAN0_IF1ARB1_R (*((volatile unsigned long *)0x40040030))
-#define CAN0_IF1ARB2_R (*((volatile unsigned long *)0x40040034))
-#define CAN0_IF1MCTL_R (*((volatile unsigned long *)0x40040038))
-#define CAN0_IF1DA1_R (*((volatile unsigned long *)0x4004003C))
-#define CAN0_IF1DA2_R (*((volatile unsigned long *)0x40040040))
-#define CAN0_IF1DB1_R (*((volatile unsigned long *)0x40040044))
-#define CAN0_IF1DB2_R (*((volatile unsigned long *)0x40040048))
-#define CAN0_IF2CRQ_R (*((volatile unsigned long *)0x40040080))
-#define CAN0_IF2CMSK_R (*((volatile unsigned long *)0x40040084))
-#define CAN0_IF2MSK1_R (*((volatile unsigned long *)0x40040088))
-#define CAN0_IF2MSK2_R (*((volatile unsigned long *)0x4004008C))
-#define CAN0_IF2ARB1_R (*((volatile unsigned long *)0x40040090))
-#define CAN0_IF2ARB2_R (*((volatile unsigned long *)0x40040094))
-#define CAN0_IF2MCTL_R (*((volatile unsigned long *)0x40040098))
-#define CAN0_IF2DA1_R (*((volatile unsigned long *)0x4004009C))
-#define CAN0_IF2DA2_R (*((volatile unsigned long *)0x400400A0))
-#define CAN0_IF2DB1_R (*((volatile unsigned long *)0x400400A4))
-#define CAN0_IF2DB2_R (*((volatile unsigned long *)0x400400A8))
-#define CAN0_TXRQ1_R (*((volatile unsigned long *)0x40040100))
-#define CAN0_TXRQ2_R (*((volatile unsigned long *)0x40040104))
-#define CAN0_NWDA1_R (*((volatile unsigned long *)0x40040120))
-#define CAN0_NWDA2_R (*((volatile unsigned long *)0x40040124))
-#define CAN0_MSG1INT_R (*((volatile unsigned long *)0x40040140))
-#define CAN0_MSG2INT_R (*((volatile unsigned long *)0x40040144))
-#define CAN0_MSG1VAL_R (*((volatile unsigned long *)0x40040160))
-#define CAN0_MSG2VAL_R (*((volatile unsigned long *)0x40040164))
-
-//*****************************************************************************
-//
-// Timer registers (WTIMER2)
-//
-//*****************************************************************************
-#define WTIMER2_CFG_R (*((volatile unsigned long *)0x4004C000))
-#define WTIMER2_TAMR_R (*((volatile unsigned long *)0x4004C004))
-#define WTIMER2_TBMR_R (*((volatile unsigned long *)0x4004C008))
-#define WTIMER2_CTL_R (*((volatile unsigned long *)0x4004C00C))
-#define WTIMER2_SYNC_R (*((volatile unsigned long *)0x4004C010))
-#define WTIMER2_IMR_R (*((volatile unsigned long *)0x4004C018))
-#define WTIMER2_RIS_R (*((volatile unsigned long *)0x4004C01C))
-#define WTIMER2_MIS_R (*((volatile unsigned long *)0x4004C020))
-#define WTIMER2_ICR_R (*((volatile unsigned long *)0x4004C024))
-#define WTIMER2_TAILR_R (*((volatile unsigned long *)0x4004C028))
-#define WTIMER2_TBILR_R (*((volatile unsigned long *)0x4004C02C))
-#define WTIMER2_TAMATCHR_R (*((volatile unsigned long *)0x4004C030))
-#define WTIMER2_TBMATCHR_R (*((volatile unsigned long *)0x4004C034))
-#define WTIMER2_TAPR_R (*((volatile unsigned long *)0x4004C038))
-#define WTIMER2_TBPR_R (*((volatile unsigned long *)0x4004C03C))
-#define WTIMER2_TAPMR_R (*((volatile unsigned long *)0x4004C040))
-#define WTIMER2_TBPMR_R (*((volatile unsigned long *)0x4004C044))
-#define WTIMER2_TAR_R (*((volatile unsigned long *)0x4004C048))
-#define WTIMER2_TBR_R (*((volatile unsigned long *)0x4004C04C))
-#define WTIMER2_TAV_R (*((volatile unsigned long *)0x4004C050))
-#define WTIMER2_TBV_R (*((volatile unsigned long *)0x4004C054))
-#define WTIMER2_RTCPD_R (*((volatile unsigned long *)0x4004C058))
-#define WTIMER2_TAPS_R (*((volatile unsigned long *)0x4004C05C))
-#define WTIMER2_TBPS_R (*((volatile unsigned long *)0x4004C060))
-#define WTIMER2_TAPV_R (*((volatile unsigned long *)0x4004C064))
-#define WTIMER2_TBPV_R (*((volatile unsigned long *)0x4004C068))
-#define WTIMER2_PP_R (*((volatile unsigned long *)0x4004CFC0))
-
-//*****************************************************************************
-//
-// Timer registers (WTIMER3)
-//
-//*****************************************************************************
-#define WTIMER3_CFG_R (*((volatile unsigned long *)0x4004D000))
-#define WTIMER3_TAMR_R (*((volatile unsigned long *)0x4004D004))
-#define WTIMER3_TBMR_R (*((volatile unsigned long *)0x4004D008))
-#define WTIMER3_CTL_R (*((volatile unsigned long *)0x4004D00C))
-#define WTIMER3_SYNC_R (*((volatile unsigned long *)0x4004D010))
-#define WTIMER3_IMR_R (*((volatile unsigned long *)0x4004D018))
-#define WTIMER3_RIS_R (*((volatile unsigned long *)0x4004D01C))
-#define WTIMER3_MIS_R (*((volatile unsigned long *)0x4004D020))
-#define WTIMER3_ICR_R (*((volatile unsigned long *)0x4004D024))
-#define WTIMER3_TAILR_R (*((volatile unsigned long *)0x4004D028))
-#define WTIMER3_TBILR_R (*((volatile unsigned long *)0x4004D02C))
-#define WTIMER3_TAMATCHR_R (*((volatile unsigned long *)0x4004D030))
-#define WTIMER3_TBMATCHR_R (*((volatile unsigned long *)0x4004D034))
-#define WTIMER3_TAPR_R (*((volatile unsigned long *)0x4004D038))
-#define WTIMER3_TBPR_R (*((volatile unsigned long *)0x4004D03C))
-#define WTIMER3_TAPMR_R (*((volatile unsigned long *)0x4004D040))
-#define WTIMER3_TBPMR_R (*((volatile unsigned long *)0x4004D044))
-#define WTIMER3_TAR_R (*((volatile unsigned long *)0x4004D048))
-#define WTIMER3_TBR_R (*((volatile unsigned long *)0x4004D04C))
-#define WTIMER3_TAV_R (*((volatile unsigned long *)0x4004D050))
-#define WTIMER3_TBV_R (*((volatile unsigned long *)0x4004D054))
-#define WTIMER3_RTCPD_R (*((volatile unsigned long *)0x4004D058))
-#define WTIMER3_TAPS_R (*((volatile unsigned long *)0x4004D05C))
-#define WTIMER3_TBPS_R (*((volatile unsigned long *)0x4004D060))
-#define WTIMER3_TAPV_R (*((volatile unsigned long *)0x4004D064))
-#define WTIMER3_TBPV_R (*((volatile unsigned long *)0x4004D068))
-#define WTIMER3_PP_R (*((volatile unsigned long *)0x4004DFC0))
-
-//*****************************************************************************
-//
-// Timer registers (WTIMER4)
-//
-//*****************************************************************************
-#define WTIMER4_CFG_R (*((volatile unsigned long *)0x4004E000))
-#define WTIMER4_TAMR_R (*((volatile unsigned long *)0x4004E004))
-#define WTIMER4_TBMR_R (*((volatile unsigned long *)0x4004E008))
-#define WTIMER4_CTL_R (*((volatile unsigned long *)0x4004E00C))
-#define WTIMER4_SYNC_R (*((volatile unsigned long *)0x4004E010))
-#define WTIMER4_IMR_R (*((volatile unsigned long *)0x4004E018))
-#define WTIMER4_RIS_R (*((volatile unsigned long *)0x4004E01C))
-#define WTIMER4_MIS_R (*((volatile unsigned long *)0x4004E020))
-#define WTIMER4_ICR_R (*((volatile unsigned long *)0x4004E024))
-#define WTIMER4_TAILR_R (*((volatile unsigned long *)0x4004E028))
-#define WTIMER4_TBILR_R (*((volatile unsigned long *)0x4004E02C))
-#define WTIMER4_TAMATCHR_R (*((volatile unsigned long *)0x4004E030))
-#define WTIMER4_TBMATCHR_R (*((volatile unsigned long *)0x4004E034))
-#define WTIMER4_TAPR_R (*((volatile unsigned long *)0x4004E038))
-#define WTIMER4_TBPR_R (*((volatile unsigned long *)0x4004E03C))
-#define WTIMER4_TAPMR_R (*((volatile unsigned long *)0x4004E040))
-#define WTIMER4_TBPMR_R (*((volatile unsigned long *)0x4004E044))
-#define WTIMER4_TAR_R (*((volatile unsigned long *)0x4004E048))
-#define WTIMER4_TBR_R (*((volatile unsigned long *)0x4004E04C))
-#define WTIMER4_TAV_R (*((volatile unsigned long *)0x4004E050))
-#define WTIMER4_TBV_R (*((volatile unsigned long *)0x4004E054))
-#define WTIMER4_RTCPD_R (*((volatile unsigned long *)0x4004E058))
-#define WTIMER4_TAPS_R (*((volatile unsigned long *)0x4004E05C))
-#define WTIMER4_TBPS_R (*((volatile unsigned long *)0x4004E060))
-#define WTIMER4_TAPV_R (*((volatile unsigned long *)0x4004E064))
-#define WTIMER4_TBPV_R (*((volatile unsigned long *)0x4004E068))
-#define WTIMER4_PP_R (*((volatile unsigned long *)0x4004EFC0))
-
-//*****************************************************************************
-//
-// Timer registers (WTIMER5)
-//
-//*****************************************************************************
-#define WTIMER5_CFG_R (*((volatile unsigned long *)0x4004F000))
-#define WTIMER5_TAMR_R (*((volatile unsigned long *)0x4004F004))
-#define WTIMER5_TBMR_R (*((volatile unsigned long *)0x4004F008))
-#define WTIMER5_CTL_R (*((volatile unsigned long *)0x4004F00C))
-#define WTIMER5_SYNC_R (*((volatile unsigned long *)0x4004F010))
-#define WTIMER5_IMR_R (*((volatile unsigned long *)0x4004F018))
-#define WTIMER5_RIS_R (*((volatile unsigned long *)0x4004F01C))
-#define WTIMER5_MIS_R (*((volatile unsigned long *)0x4004F020))
-#define WTIMER5_ICR_R (*((volatile unsigned long *)0x4004F024))
-#define WTIMER5_TAILR_R (*((volatile unsigned long *)0x4004F028))
-#define WTIMER5_TBILR_R (*((volatile unsigned long *)0x4004F02C))
-#define WTIMER5_TAMATCHR_R (*((volatile unsigned long *)0x4004F030))
-#define WTIMER5_TBMATCHR_R (*((volatile unsigned long *)0x4004F034))
-#define WTIMER5_TAPR_R (*((volatile unsigned long *)0x4004F038))
-#define WTIMER5_TBPR_R (*((volatile unsigned long *)0x4004F03C))
-#define WTIMER5_TAPMR_R (*((volatile unsigned long *)0x4004F040))
-#define WTIMER5_TBPMR_R (*((volatile unsigned long *)0x4004F044))
-#define WTIMER5_TAR_R (*((volatile unsigned long *)0x4004F048))
-#define WTIMER5_TBR_R (*((volatile unsigned long *)0x4004F04C))
-#define WTIMER5_TAV_R (*((volatile unsigned long *)0x4004F050))
-#define WTIMER5_TBV_R (*((volatile unsigned long *)0x4004F054))
-#define WTIMER5_RTCPD_R (*((volatile unsigned long *)0x4004F058))
-#define WTIMER5_TAPS_R (*((volatile unsigned long *)0x4004F05C))
-#define WTIMER5_TBPS_R (*((volatile unsigned long *)0x4004F060))
-#define WTIMER5_TAPV_R (*((volatile unsigned long *)0x4004F064))
-#define WTIMER5_TBPV_R (*((volatile unsigned long *)0x4004F068))
-#define WTIMER5_PP_R (*((volatile unsigned long *)0x4004FFC0))
-
-//*****************************************************************************
-//
-// Univeral Serial Bus registers (USB0)
-//
-//*****************************************************************************
-#define USB0_FADDR_R (*((volatile unsigned char *)0x40050000))
-#define USB0_POWER_R (*((volatile unsigned char *)0x40050001))
-#define USB0_TXIS_R (*((volatile unsigned short *)0x40050002))
-#define USB0_RXIS_R (*((volatile unsigned short *)0x40050004))
-#define USB0_TXIE_R (*((volatile unsigned short *)0x40050006))
-#define USB0_RXIE_R (*((volatile unsigned short *)0x40050008))
-#define USB0_IS_R (*((volatile unsigned char *)0x4005000A))
-#define USB0_IE_R (*((volatile unsigned char *)0x4005000B))
-#define USB0_FRAME_R (*((volatile unsigned short *)0x4005000C))
-#define USB0_EPIDX_R (*((volatile unsigned char *)0x4005000E))
-#define USB0_TEST_R (*((volatile unsigned char *)0x4005000F))
-#define USB0_FIFO0_R (*((volatile unsigned long *)0x40050020))
-#define USB0_FIFO1_R (*((volatile unsigned long *)0x40050024))
-#define USB0_FIFO2_R (*((volatile unsigned long *)0x40050028))
-#define USB0_FIFO3_R (*((volatile unsigned long *)0x4005002C))
-#define USB0_FIFO4_R (*((volatile unsigned long *)0x40050030))
-#define USB0_FIFO5_R (*((volatile unsigned long *)0x40050034))
-#define USB0_FIFO6_R (*((volatile unsigned long *)0x40050038))
-#define USB0_FIFO7_R (*((volatile unsigned long *)0x4005003C))
-#define USB0_TXFIFOSZ_R (*((volatile unsigned char *)0x40050062))
-#define USB0_RXFIFOSZ_R (*((volatile unsigned char *)0x40050063))
-#define USB0_TXFIFOADD_R (*((volatile unsigned short *)0x40050064))
-#define USB0_RXFIFOADD_R (*((volatile unsigned short *)0x40050066))
-#define USB0_CONTIM_R (*((volatile unsigned char *)0x4005007A))
-#define USB0_FSEOF_R (*((volatile unsigned char *)0x4005007D))
-#define USB0_LSEOF_R (*((volatile unsigned char *)0x4005007E))
-#define USB0_CSRL0_R (*((volatile unsigned char *)0x40050102))
-#define USB0_CSRH0_R (*((volatile unsigned char *)0x40050103))
-#define USB0_COUNT0_R (*((volatile unsigned char *)0x40050108))
-#define USB0_TXMAXP1_R (*((volatile unsigned short *)0x40050110))
-#define USB0_TXCSRL1_R (*((volatile unsigned char *)0x40050112))
-#define USB0_TXCSRH1_R (*((volatile unsigned char *)0x40050113))
-#define USB0_RXMAXP1_R (*((volatile unsigned short *)0x40050114))
-#define USB0_RXCSRL1_R (*((volatile unsigned char *)0x40050116))
-#define USB0_RXCSRH1_R (*((volatile unsigned char *)0x40050117))
-#define USB0_RXCOUNT1_R (*((volatile unsigned short *)0x40050118))
-#define USB0_TXMAXP2_R (*((volatile unsigned short *)0x40050120))
-#define USB0_TXCSRL2_R (*((volatile unsigned char *)0x40050122))
-#define USB0_TXCSRH2_R (*((volatile unsigned char *)0x40050123))
-#define USB0_RXMAXP2_R (*((volatile unsigned short *)0x40050124))
-#define USB0_RXCSRL2_R (*((volatile unsigned char *)0x40050126))
-#define USB0_RXCSRH2_R (*((volatile unsigned char *)0x40050127))
-#define USB0_RXCOUNT2_R (*((volatile unsigned short *)0x40050128))
-#define USB0_TXMAXP3_R (*((volatile unsigned short *)0x40050130))
-#define USB0_TXCSRL3_R (*((volatile unsigned char *)0x40050132))
-#define USB0_TXCSRH3_R (*((volatile unsigned char *)0x40050133))
-#define USB0_RXMAXP3_R (*((volatile unsigned short *)0x40050134))
-#define USB0_RXCSRL3_R (*((volatile unsigned char *)0x40050136))
-#define USB0_RXCSRH3_R (*((volatile unsigned char *)0x40050137))
-#define USB0_RXCOUNT3_R (*((volatile unsigned short *)0x40050138))
-#define USB0_TXMAXP4_R (*((volatile unsigned short *)0x40050140))
-#define USB0_TXCSRL4_R (*((volatile unsigned char *)0x40050142))
-#define USB0_TXCSRH4_R (*((volatile unsigned char *)0x40050143))
-#define USB0_RXMAXP4_R (*((volatile unsigned short *)0x40050144))
-#define USB0_RXCSRL4_R (*((volatile unsigned char *)0x40050146))
-#define USB0_RXCSRH4_R (*((volatile unsigned char *)0x40050147))
-#define USB0_RXCOUNT4_R (*((volatile unsigned short *)0x40050148))
-#define USB0_TXMAXP5_R (*((volatile unsigned short *)0x40050150))
-#define USB0_TXCSRL5_R (*((volatile unsigned char *)0x40050152))
-#define USB0_TXCSRH5_R (*((volatile unsigned char *)0x40050153))
-#define USB0_RXMAXP5_R (*((volatile unsigned short *)0x40050154))
-#define USB0_RXCSRL5_R (*((volatile unsigned char *)0x40050156))
-#define USB0_RXCSRH5_R (*((volatile unsigned char *)0x40050157))
-#define USB0_RXCOUNT5_R (*((volatile unsigned short *)0x40050158))
-#define USB0_TXMAXP6_R (*((volatile unsigned short *)0x40050160))
-#define USB0_TXCSRL6_R (*((volatile unsigned char *)0x40050162))
-#define USB0_TXCSRH6_R (*((volatile unsigned char *)0x40050163))
-#define USB0_RXMAXP6_R (*((volatile unsigned short *)0x40050164))
-#define USB0_RXCSRL6_R (*((volatile unsigned char *)0x40050166))
-#define USB0_RXCSRH6_R (*((volatile unsigned char *)0x40050167))
-#define USB0_RXCOUNT6_R (*((volatile unsigned short *)0x40050168))
-#define USB0_TXMAXP7_R (*((volatile unsigned short *)0x40050170))
-#define USB0_TXCSRL7_R (*((volatile unsigned char *)0x40050172))
-#define USB0_TXCSRH7_R (*((volatile unsigned char *)0x40050173))
-#define USB0_RXMAXP7_R (*((volatile unsigned short *)0x40050174))
-#define USB0_RXCSRL7_R (*((volatile unsigned char *)0x40050176))
-#define USB0_RXCSRH7_R (*((volatile unsigned char *)0x40050177))
-#define USB0_RXCOUNT7_R (*((volatile unsigned short *)0x40050178))
-#define USB0_RXDPKTBUFDIS_R (*((volatile unsigned short *)0x40050340))
-#define USB0_TXDPKTBUFDIS_R (*((volatile unsigned short *)0x40050342))
-#define USB0_DRRIS_R (*((volatile unsigned long *)0x40050410))
-#define USB0_DRIM_R (*((volatile unsigned long *)0x40050414))
-#define USB0_DRISC_R (*((volatile unsigned long *)0x40050418))
-#define USB0_DMASEL_R (*((volatile unsigned long *)0x40050450))
-#define USB0_PP_R (*((volatile unsigned long *)0x40050FC0))
-
-//*****************************************************************************
-//
-// GPIO registers (PORTA AHB)
-//
-//*****************************************************************************
-#define GPIO_PORTA_AHB_DATA_BITS_R \
- ((volatile unsigned long *)0x40058000)
-#define GPIO_PORTA_AHB_DATA_R (*((volatile unsigned long *)0x400583FC))
-#define GPIO_PORTA_AHB_DIR_R (*((volatile unsigned long *)0x40058400))
-#define GPIO_PORTA_AHB_IS_R (*((volatile unsigned long *)0x40058404))
-#define GPIO_PORTA_AHB_IBE_R (*((volatile unsigned long *)0x40058408))
-#define GPIO_PORTA_AHB_IEV_R (*((volatile unsigned long *)0x4005840C))
-#define GPIO_PORTA_AHB_IM_R (*((volatile unsigned long *)0x40058410))
-#define GPIO_PORTA_AHB_RIS_R (*((volatile unsigned long *)0x40058414))
-#define GPIO_PORTA_AHB_MIS_R (*((volatile unsigned long *)0x40058418))
-#define GPIO_PORTA_AHB_ICR_R (*((volatile unsigned long *)0x4005841C))
-#define GPIO_PORTA_AHB_AFSEL_R (*((volatile unsigned long *)0x40058420))
-#define GPIO_PORTA_AHB_DR2R_R (*((volatile unsigned long *)0x40058500))
-#define GPIO_PORTA_AHB_DR4R_R (*((volatile unsigned long *)0x40058504))
-#define GPIO_PORTA_AHB_DR8R_R (*((volatile unsigned long *)0x40058508))
-#define GPIO_PORTA_AHB_ODR_R (*((volatile unsigned long *)0x4005850C))
-#define GPIO_PORTA_AHB_PUR_R (*((volatile unsigned long *)0x40058510))
-#define GPIO_PORTA_AHB_PDR_R (*((volatile unsigned long *)0x40058514))
-#define GPIO_PORTA_AHB_SLR_R (*((volatile unsigned long *)0x40058518))
-#define GPIO_PORTA_AHB_DEN_R (*((volatile unsigned long *)0x4005851C))
-#define GPIO_PORTA_AHB_LOCK_R (*((volatile unsigned long *)0x40058520))
-#define GPIO_PORTA_AHB_CR_R (*((volatile unsigned long *)0x40058524))
-#define GPIO_PORTA_AHB_AMSEL_R (*((volatile unsigned long *)0x40058528))
-#define GPIO_PORTA_AHB_PCTL_R (*((volatile unsigned long *)0x4005852C))
-#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile unsigned long *)0x40058530))
-#define GPIO_PORTA_AHB_DMACTL_R (*((volatile unsigned long *)0x40058534))
-#define GPIO_PORTA_AHB_SI_R (*((volatile unsigned long *)0x40058538))
-
-//*****************************************************************************
-//
-// GPIO registers (PORTB AHB)
-//
-//*****************************************************************************
-#define GPIO_PORTB_AHB_DATA_BITS_R \
- ((volatile unsigned long *)0x40059000)
-#define GPIO_PORTB_AHB_DATA_R (*((volatile unsigned long *)0x400593FC))
-#define GPIO_PORTB_AHB_DIR_R (*((volatile unsigned long *)0x40059400))
-#define GPIO_PORTB_AHB_IS_R (*((volatile unsigned long *)0x40059404))
-#define GPIO_PORTB_AHB_IBE_R (*((volatile unsigned long *)0x40059408))
-#define GPIO_PORTB_AHB_IEV_R (*((volatile unsigned long *)0x4005940C))
-#define GPIO_PORTB_AHB_IM_R (*((volatile unsigned long *)0x40059410))
-#define GPIO_PORTB_AHB_RIS_R (*((volatile unsigned long *)0x40059414))
-#define GPIO_PORTB_AHB_MIS_R (*((volatile unsigned long *)0x40059418))
-#define GPIO_PORTB_AHB_ICR_R (*((volatile unsigned long *)0x4005941C))
-#define GPIO_PORTB_AHB_AFSEL_R (*((volatile unsigned long *)0x40059420))
-#define GPIO_PORTB_AHB_DR2R_R (*((volatile unsigned long *)0x40059500))
-#define GPIO_PORTB_AHB_DR4R_R (*((volatile unsigned long *)0x40059504))
-#define GPIO_PORTB_AHB_DR8R_R (*((volatile unsigned long *)0x40059508))
-#define GPIO_PORTB_AHB_ODR_R (*((volatile unsigned long *)0x4005950C))
-#define GPIO_PORTB_AHB_PUR_R (*((volatile unsigned long *)0x40059510))
-#define GPIO_PORTB_AHB_PDR_R (*((volatile unsigned long *)0x40059514))
-#define GPIO_PORTB_AHB_SLR_R (*((volatile unsigned long *)0x40059518))
-#define GPIO_PORTB_AHB_DEN_R (*((volatile unsigned long *)0x4005951C))
-#define GPIO_PORTB_AHB_LOCK_R (*((volatile unsigned long *)0x40059520))
-#define GPIO_PORTB_AHB_CR_R (*((volatile unsigned long *)0x40059524))
-#define GPIO_PORTB_AHB_AMSEL_R (*((volatile unsigned long *)0x40059528))
-#define GPIO_PORTB_AHB_PCTL_R (*((volatile unsigned long *)0x4005952C))
-#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile unsigned long *)0x40059530))
-#define GPIO_PORTB_AHB_DMACTL_R (*((volatile unsigned long *)0x40059534))
-#define GPIO_PORTB_AHB_SI_R (*((volatile unsigned long *)0x40059538))
-
-//*****************************************************************************
-//
-// GPIO registers (PORTC AHB)
-//
-//*****************************************************************************
-#define GPIO_PORTC_AHB_DATA_BITS_R \
- ((volatile unsigned long *)0x4005A000)
-#define GPIO_PORTC_AHB_DATA_R (*((volatile unsigned long *)0x4005A3FC))
-#define GPIO_PORTC_AHB_DIR_R (*((volatile unsigned long *)0x4005A400))
-#define GPIO_PORTC_AHB_IS_R (*((volatile unsigned long *)0x4005A404))
-#define GPIO_PORTC_AHB_IBE_R (*((volatile unsigned long *)0x4005A408))
-#define GPIO_PORTC_AHB_IEV_R (*((volatile unsigned long *)0x4005A40C))
-#define GPIO_PORTC_AHB_IM_R (*((volatile unsigned long *)0x4005A410))
-#define GPIO_PORTC_AHB_RIS_R (*((volatile unsigned long *)0x4005A414))
-#define GPIO_PORTC_AHB_MIS_R (*((volatile unsigned long *)0x4005A418))
-#define GPIO_PORTC_AHB_ICR_R (*((volatile unsigned long *)0x4005A41C))
-#define GPIO_PORTC_AHB_AFSEL_R (*((volatile unsigned long *)0x4005A420))
-#define GPIO_PORTC_AHB_DR2R_R (*((volatile unsigned long *)0x4005A500))
-#define GPIO_PORTC_AHB_DR4R_R (*((volatile unsigned long *)0x4005A504))
-#define GPIO_PORTC_AHB_DR8R_R (*((volatile unsigned long *)0x4005A508))
-#define GPIO_PORTC_AHB_ODR_R (*((volatile unsigned long *)0x4005A50C))
-#define GPIO_PORTC_AHB_PUR_R (*((volatile unsigned long *)0x4005A510))
-#define GPIO_PORTC_AHB_PDR_R (*((volatile unsigned long *)0x4005A514))
-#define GPIO_PORTC_AHB_SLR_R (*((volatile unsigned long *)0x4005A518))
-#define GPIO_PORTC_AHB_DEN_R (*((volatile unsigned long *)0x4005A51C))
-#define GPIO_PORTC_AHB_LOCK_R (*((volatile unsigned long *)0x4005A520))
-#define GPIO_PORTC_AHB_CR_R (*((volatile unsigned long *)0x4005A524))
-#define GPIO_PORTC_AHB_AMSEL_R (*((volatile unsigned long *)0x4005A528))
-#define GPIO_PORTC_AHB_PCTL_R (*((volatile unsigned long *)0x4005A52C))
-#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005A530))
-#define GPIO_PORTC_AHB_DMACTL_R (*((volatile unsigned long *)0x4005A534))
-#define GPIO_PORTC_AHB_SI_R (*((volatile unsigned long *)0x4005A538))
-
-//*****************************************************************************
-//
-// GPIO registers (PORTD AHB)
-//
-//*****************************************************************************
-#define GPIO_PORTD_AHB_DATA_BITS_R \
- ((volatile unsigned long *)0x4005B000)
-#define GPIO_PORTD_AHB_DATA_R (*((volatile unsigned long *)0x4005B3FC))
-#define GPIO_PORTD_AHB_DIR_R (*((volatile unsigned long *)0x4005B400))
-#define GPIO_PORTD_AHB_IS_R (*((volatile unsigned long *)0x4005B404))
-#define GPIO_PORTD_AHB_IBE_R (*((volatile unsigned long *)0x4005B408))
-#define GPIO_PORTD_AHB_IEV_R (*((volatile unsigned long *)0x4005B40C))
-#define GPIO_PORTD_AHB_IM_R (*((volatile unsigned long *)0x4005B410))
-#define GPIO_PORTD_AHB_RIS_R (*((volatile unsigned long *)0x4005B414))
-#define GPIO_PORTD_AHB_MIS_R (*((volatile unsigned long *)0x4005B418))
-#define GPIO_PORTD_AHB_ICR_R (*((volatile unsigned long *)0x4005B41C))
-#define GPIO_PORTD_AHB_AFSEL_R (*((volatile unsigned long *)0x4005B420))
-#define GPIO_PORTD_AHB_DR2R_R (*((volatile unsigned long *)0x4005B500))
-#define GPIO_PORTD_AHB_DR4R_R (*((volatile unsigned long *)0x4005B504))
-#define GPIO_PORTD_AHB_DR8R_R (*((volatile unsigned long *)0x4005B508))
-#define GPIO_PORTD_AHB_ODR_R (*((volatile unsigned long *)0x4005B50C))
-#define GPIO_PORTD_AHB_PUR_R (*((volatile unsigned long *)0x4005B510))
-#define GPIO_PORTD_AHB_PDR_R (*((volatile unsigned long *)0x4005B514))
-#define GPIO_PORTD_AHB_SLR_R (*((volatile unsigned long *)0x4005B518))
-#define GPIO_PORTD_AHB_DEN_R (*((volatile unsigned long *)0x4005B51C))
-#define GPIO_PORTD_AHB_LOCK_R (*((volatile unsigned long *)0x4005B520))
-#define GPIO_PORTD_AHB_CR_R (*((volatile unsigned long *)0x4005B524))
-#define GPIO_PORTD_AHB_AMSEL_R (*((volatile unsigned long *)0x4005B528))
-#define GPIO_PORTD_AHB_PCTL_R (*((volatile unsigned long *)0x4005B52C))
-#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005B530))
-#define GPIO_PORTD_AHB_DMACTL_R (*((volatile unsigned long *)0x4005B534))
-#define GPIO_PORTD_AHB_SI_R (*((volatile unsigned long *)0x4005B538))
-
-//*****************************************************************************
-//
-// GPIO registers (PORTE AHB)
-//
-//*****************************************************************************
-#define GPIO_PORTE_AHB_DATA_BITS_R \
- ((volatile unsigned long *)0x4005C000)
-#define GPIO_PORTE_AHB_DATA_R (*((volatile unsigned long *)0x4005C3FC))
-#define GPIO_PORTE_AHB_DIR_R (*((volatile unsigned long *)0x4005C400))
-#define GPIO_PORTE_AHB_IS_R (*((volatile unsigned long *)0x4005C404))
-#define GPIO_PORTE_AHB_IBE_R (*((volatile unsigned long *)0x4005C408))
-#define GPIO_PORTE_AHB_IEV_R (*((volatile unsigned long *)0x4005C40C))
-#define GPIO_PORTE_AHB_IM_R (*((volatile unsigned long *)0x4005C410))
-#define GPIO_PORTE_AHB_RIS_R (*((volatile unsigned long *)0x4005C414))
-#define GPIO_PORTE_AHB_MIS_R (*((volatile unsigned long *)0x4005C418))
-#define GPIO_PORTE_AHB_ICR_R (*((volatile unsigned long *)0x4005C41C))
-#define GPIO_PORTE_AHB_AFSEL_R (*((volatile unsigned long *)0x4005C420))
-#define GPIO_PORTE_AHB_DR2R_R (*((volatile unsigned long *)0x4005C500))
-#define GPIO_PORTE_AHB_DR4R_R (*((volatile unsigned long *)0x4005C504))
-#define GPIO_PORTE_AHB_DR8R_R (*((volatile unsigned long *)0x4005C508))
-#define GPIO_PORTE_AHB_ODR_R (*((volatile unsigned long *)0x4005C50C))
-#define GPIO_PORTE_AHB_PUR_R (*((volatile unsigned long *)0x4005C510))
-#define GPIO_PORTE_AHB_PDR_R (*((volatile unsigned long *)0x4005C514))
-#define GPIO_PORTE_AHB_SLR_R (*((volatile unsigned long *)0x4005C518))
-#define GPIO_PORTE_AHB_DEN_R (*((volatile unsigned long *)0x4005C51C))
-#define GPIO_PORTE_AHB_LOCK_R (*((volatile unsigned long *)0x4005C520))
-#define GPIO_PORTE_AHB_CR_R (*((volatile unsigned long *)0x4005C524))
-#define GPIO_PORTE_AHB_AMSEL_R (*((volatile unsigned long *)0x4005C528))
-#define GPIO_PORTE_AHB_PCTL_R (*((volatile unsigned long *)0x4005C52C))
-#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005C530))
-#define GPIO_PORTE_AHB_DMACTL_R (*((volatile unsigned long *)0x4005C534))
-#define GPIO_PORTE_AHB_SI_R (*((volatile unsigned long *)0x4005C538))
-
-//*****************************************************************************
-//
-// GPIO registers (PORTF AHB)
-//
-//*****************************************************************************
-#define GPIO_PORTF_AHB_DATA_BITS_R \
- ((volatile unsigned long *)0x4005D000)
-#define GPIO_PORTF_AHB_DATA_R (*((volatile unsigned long *)0x4005D3FC))
-#define GPIO_PORTF_AHB_DIR_R (*((volatile unsigned long *)0x4005D400))
-#define GPIO_PORTF_AHB_IS_R (*((volatile unsigned long *)0x4005D404))
-#define GPIO_PORTF_AHB_IBE_R (*((volatile unsigned long *)0x4005D408))
-#define GPIO_PORTF_AHB_IEV_R (*((volatile unsigned long *)0x4005D40C))
-#define GPIO_PORTF_AHB_IM_R (*((volatile unsigned long *)0x4005D410))
-#define GPIO_PORTF_AHB_RIS_R (*((volatile unsigned long *)0x4005D414))
-#define GPIO_PORTF_AHB_MIS_R (*((volatile unsigned long *)0x4005D418))
-#define GPIO_PORTF_AHB_ICR_R (*((volatile unsigned long *)0x4005D41C))
-#define GPIO_PORTF_AHB_AFSEL_R (*((volatile unsigned long *)0x4005D420))
-#define GPIO_PORTF_AHB_DR2R_R (*((volatile unsigned long *)0x4005D500))
-#define GPIO_PORTF_AHB_DR4R_R (*((volatile unsigned long *)0x4005D504))
-#define GPIO_PORTF_AHB_DR8R_R (*((volatile unsigned long *)0x4005D508))
-#define GPIO_PORTF_AHB_ODR_R (*((volatile unsigned long *)0x4005D50C))
-#define GPIO_PORTF_AHB_PUR_R (*((volatile unsigned long *)0x4005D510))
-#define GPIO_PORTF_AHB_PDR_R (*((volatile unsigned long *)0x4005D514))
-#define GPIO_PORTF_AHB_SLR_R (*((volatile unsigned long *)0x4005D518))
-#define GPIO_PORTF_AHB_DEN_R (*((volatile unsigned long *)0x4005D51C))
-#define GPIO_PORTF_AHB_LOCK_R (*((volatile unsigned long *)0x4005D520))
-#define GPIO_PORTF_AHB_CR_R (*((volatile unsigned long *)0x4005D524))
-#define GPIO_PORTF_AHB_AMSEL_R (*((volatile unsigned long *)0x4005D528))
-#define GPIO_PORTF_AHB_PCTL_R (*((volatile unsigned long *)0x4005D52C))
-#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005D530))
-#define GPIO_PORTF_AHB_DMACTL_R (*((volatile unsigned long *)0x4005D534))
-#define GPIO_PORTF_AHB_SI_R (*((volatile unsigned long *)0x4005D538))
-
-//*****************************************************************************
-//
-// EEPROM registers (EEPROM)
-//
-//*****************************************************************************
-#define EEPROM_EESIZE_R (*((volatile unsigned long *)0x400AF000))
-#define EEPROM_EEBLOCK_R (*((volatile unsigned long *)0x400AF004))
-#define EEPROM_EEOFFSET_R (*((volatile unsigned long *)0x400AF008))
-#define EEPROM_EERDWR_R (*((volatile unsigned long *)0x400AF010))
-#define EEPROM_EERDWRINC_R (*((volatile unsigned long *)0x400AF014))
-#define EEPROM_EEDONE_R (*((volatile unsigned long *)0x400AF018))
-#define EEPROM_EESUPP_R (*((volatile unsigned long *)0x400AF01C))
-#define EEPROM_EEUNLOCK_R (*((volatile unsigned long *)0x400AF020))
-#define EEPROM_EEPROT_R (*((volatile unsigned long *)0x400AF030))
-#define EEPROM_EEPASS0_R (*((volatile unsigned long *)0x400AF034))
-#define EEPROM_EEPASS1_R (*((volatile unsigned long *)0x400AF038))
-#define EEPROM_EEPASS2_R (*((volatile unsigned long *)0x400AF03C))
-#define EEPROM_EEINT_R (*((volatile unsigned long *)0x400AF040))
-#define EEPROM_EEHIDE_R (*((volatile unsigned long *)0x400AF050))
-#define EEPROM_EEDBGME_R (*((volatile unsigned long *)0x400AF080))
-#define EEPROM_PP_R (*((volatile unsigned long *)0x400AFFC0))
-
-//*****************************************************************************
-//
-// System Exception Module registers (SYSEXC)
-//
-//*****************************************************************************
-#define SYSEXC_RIS_R (*((volatile unsigned long *)0x400F9000))
-#define SYSEXC_IM_R (*((volatile unsigned long *)0x400F9004))
-#define SYSEXC_MIS_R (*((volatile unsigned long *)0x400F9008))
-#define SYSEXC_IC_R (*((volatile unsigned long *)0x400F900C))
-
-//*****************************************************************************
-//
-// Hibernation module registers (HIB)
-//
-//*****************************************************************************
-#define HIB_RTCC_R (*((volatile unsigned long *)0x400FC000))
-#define HIB_RTCM0_R (*((volatile unsigned long *)0x400FC004))
-#define HIB_RTCLD_R (*((volatile unsigned long *)0x400FC00C))
-#define HIB_CTL_R (*((volatile unsigned long *)0x400FC010))
-#define HIB_IM_R (*((volatile unsigned long *)0x400FC014))
-#define HIB_RIS_R (*((volatile unsigned long *)0x400FC018))
-#define HIB_MIS_R (*((volatile unsigned long *)0x400FC01C))
-#define HIB_IC_R (*((volatile unsigned long *)0x400FC020))
-#define HIB_RTCT_R (*((volatile unsigned long *)0x400FC024))
-#define HIB_RTCSS_R (*((volatile unsigned long *)0x400FC028))
-#define HIB_DATA_R (*((volatile unsigned long *)0x400FC030))
-
-//*****************************************************************************
-//
-// FLASH registers (FLASH CTRL)
-//
-//*****************************************************************************
-#define FLASH_FMA_R (*((volatile unsigned long *)0x400FD000))
-#define FLASH_FMD_R (*((volatile unsigned long *)0x400FD004))
-#define FLASH_FMC_R (*((volatile unsigned long *)0x400FD008))
-#define FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C))
-#define FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010))
-#define FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014))
-#define FLASH_FMC2_R (*((volatile unsigned long *)0x400FD020))
-#define FLASH_FWBVAL_R (*((volatile unsigned long *)0x400FD030))
-#define FLASH_FWBN_R (*((volatile unsigned long *)0x400FD100))
-#define FLASH_FSIZE_R (*((volatile unsigned long *)0x400FDFC0))
-#define FLASH_SSIZE_R (*((volatile unsigned long *)0x400FDFC4))
-#define FLASH_ROMSWMAP_R (*((volatile unsigned long *)0x400FDFCC))
-#define FLASH_RMCTL_R (*((volatile unsigned long *)0x400FE0F0))
-#define FLASH_BOOTCFG_R (*((volatile unsigned long *)0x400FE1D0))
-#define FLASH_USERREG0_R (*((volatile unsigned long *)0x400FE1E0))
-#define FLASH_USERREG1_R (*((volatile unsigned long *)0x400FE1E4))
-#define FLASH_USERREG2_R (*((volatile unsigned long *)0x400FE1E8))
-#define FLASH_USERREG3_R (*((volatile unsigned long *)0x400FE1EC))
-#define FLASH_FMPRE0_R (*((volatile unsigned long *)0x400FE200))
-#define FLASH_FMPRE1_R (*((volatile unsigned long *)0x400FE204))
-#define FLASH_FMPRE2_R (*((volatile unsigned long *)0x400FE208))
-#define FLASH_FMPRE3_R (*((volatile unsigned long *)0x400FE20C))
-#define FLASH_FMPPE0_R (*((volatile unsigned long *)0x400FE400))
-#define FLASH_FMPPE1_R (*((volatile unsigned long *)0x400FE404))
-#define FLASH_FMPPE2_R (*((volatile unsigned long *)0x400FE408))
-#define FLASH_FMPPE3_R (*((volatile unsigned long *)0x400FE40C))
-
-//*****************************************************************************
-//
-// System Control registers (SYSCTL)
-//
-//*****************************************************************************
-#define SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000))
-#define SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004))
-#define SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008))
-#define SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010))
-#define SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014))
-#define SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018))
-#define SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C))
-#define SYSCTL_DC5_R (*((volatile unsigned long *)0x400FE020))
-#define SYSCTL_DC6_R (*((volatile unsigned long *)0x400FE024))
-#define SYSCTL_DC7_R (*((volatile unsigned long *)0x400FE028))
-#define SYSCTL_DC8_R (*((volatile unsigned long *)0x400FE02C))
-#define SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030))
-#define SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040))
-#define SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044))
-#define SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048))
-#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))
-#define SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054))
-#define SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058))
-#define SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C))
-#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))
-#define SYSCTL_GPIOHBCTL_R (*((volatile unsigned long *)0x400FE06C))
-#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))
-#define SYSCTL_MOSCCTL_R (*((volatile unsigned long *)0x400FE07C))
-#define SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100))
-#define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104))
-#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108))
-#define SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110))
-#define SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114))
-#define SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118))
-#define SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120))
-#define SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124))
-#define SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128))
-#define SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144))
-#define SYSCTL_SYSPROP_R (*((volatile unsigned long *)0x400FE14C))
-#define SYSCTL_PIOSCCAL_R (*((volatile unsigned long *)0x400FE150))
-#define SYSCTL_PIOSCSTAT_R (*((volatile unsigned long *)0x400FE154))
-#define SYSCTL_PLLFREQ0_R (*((volatile unsigned long *)0x400FE160))
-#define SYSCTL_PLLFREQ1_R (*((volatile unsigned long *)0x400FE164))
-#define SYSCTL_PLLSTAT_R (*((volatile unsigned long *)0x400FE168))
-#define SYSCTL_DC9_R (*((volatile unsigned long *)0x400FE190))
-#define SYSCTL_NVMSTAT_R (*((volatile unsigned long *)0x400FE1A0))
-#define SYSCTL_PPWD_R (*((volatile unsigned long *)0x400FE300))
-#define SYSCTL_PPTIMER_R (*((volatile unsigned long *)0x400FE304))
-#define SYSCTL_PPGPIO_R (*((volatile unsigned long *)0x400FE308))
-#define SYSCTL_PPDMA_R (*((volatile unsigned long *)0x400FE30C))
-#define SYSCTL_PPHIB_R (*((volatile unsigned long *)0x400FE314))
-#define SYSCTL_PPUART_R (*((volatile unsigned long *)0x400FE318))
-#define SYSCTL_PPSSI_R (*((volatile unsigned long *)0x400FE31C))
-#define SYSCTL_PPI2C_R (*((volatile unsigned long *)0x400FE320))
-#define SYSCTL_PPUSB_R (*((volatile unsigned long *)0x400FE328))
-#define SYSCTL_PPCAN_R (*((volatile unsigned long *)0x400FE334))
-#define SYSCTL_PPADC_R (*((volatile unsigned long *)0x400FE338))
-#define SYSCTL_PPACMP_R (*((volatile unsigned long *)0x400FE33C))
-#define SYSCTL_PPPWM_R (*((volatile unsigned long *)0x400FE340))
-#define SYSCTL_PPQEI_R (*((volatile unsigned long *)0x400FE344))
-#define SYSCTL_PPEEPROM_R (*((volatile unsigned long *)0x400FE358))
-#define SYSCTL_PPWTIMER_R (*((volatile unsigned long *)0x400FE35C))
-#define SYSCTL_SRWD_R (*((volatile unsigned long *)0x400FE500))
-#define SYSCTL_SRTIMER_R (*((volatile unsigned long *)0x400FE504))
-#define SYSCTL_SRGPIO_R (*((volatile unsigned long *)0x400FE508))
-#define SYSCTL_SRDMA_R (*((volatile unsigned long *)0x400FE50C))
-#define SYSCTL_SRHIB_R (*((volatile unsigned long *)0x400FE514))
-#define SYSCTL_SRUART_R (*((volatile unsigned long *)0x400FE518))
-#define SYSCTL_SRSSI_R (*((volatile unsigned long *)0x400FE51C))
-#define SYSCTL_SRI2C_R (*((volatile unsigned long *)0x400FE520))
-#define SYSCTL_SRUSB_R (*((volatile unsigned long *)0x400FE528))
-#define SYSCTL_SRCAN_R (*((volatile unsigned long *)0x400FE534))
-#define SYSCTL_SRADC_R (*((volatile unsigned long *)0x400FE538))
-#define SYSCTL_SRACMP_R (*((volatile unsigned long *)0x400FE53C))
-#define SYSCTL_SREEPROM_R (*((volatile unsigned long *)0x400FE558))
-#define SYSCTL_SRWTIMER_R (*((volatile unsigned long *)0x400FE55C))
-#define SYSCTL_RCGCWD_R (*((volatile unsigned long *)0x400FE600))
-#define SYSCTL_RCGCTIMER_R (*((volatile unsigned long *)0x400FE604))
-#define SYSCTL_RCGCGPIO_R (*((volatile unsigned long *)0x400FE608))
-#define SYSCTL_RCGCDMA_R (*((volatile unsigned long *)0x400FE60C))
-#define SYSCTL_RCGCHIB_R (*((volatile unsigned long *)0x400FE614))
-#define SYSCTL_RCGCUART_R (*((volatile unsigned long *)0x400FE618))
-#define SYSCTL_RCGCSSI_R (*((volatile unsigned long *)0x400FE61C))
-#define SYSCTL_RCGCI2C_R (*((volatile unsigned long *)0x400FE620))
-#define SYSCTL_RCGCUSB_R (*((volatile unsigned long *)0x400FE628))
-#define SYSCTL_RCGCCAN_R (*((volatile unsigned long *)0x400FE634))
-#define SYSCTL_RCGCADC_R (*((volatile unsigned long *)0x400FE638))
-#define SYSCTL_RCGCACMP_R (*((volatile unsigned long *)0x400FE63C))
-#define SYSCTL_RCGCEEPROM_R (*((volatile unsigned long *)0x400FE658))
-#define SYSCTL_RCGCWTIMER_R (*((volatile unsigned long *)0x400FE65C))
-#define SYSCTL_SCGCWD_R (*((volatile unsigned long *)0x400FE700))
-#define SYSCTL_SCGCTIMER_R (*((volatile unsigned long *)0x400FE704))
-#define SYSCTL_SCGCGPIO_R (*((volatile unsigned long *)0x400FE708))
-#define SYSCTL_SCGCDMA_R (*((volatile unsigned long *)0x400FE70C))
-#define SYSCTL_SCGCHIB_R (*((volatile unsigned long *)0x400FE714))
-#define SYSCTL_SCGCUART_R (*((volatile unsigned long *)0x400FE718))
-#define SYSCTL_SCGCSSI_R (*((volatile unsigned long *)0x400FE71C))
-#define SYSCTL_SCGCI2C_R (*((volatile unsigned long *)0x400FE720))
-#define SYSCTL_SCGCUSB_R (*((volatile unsigned long *)0x400FE728))
-#define SYSCTL_SCGCCAN_R (*((volatile unsigned long *)0x400FE734))
-#define SYSCTL_SCGCADC_R (*((volatile unsigned long *)0x400FE738))
-#define SYSCTL_SCGCACMP_R (*((volatile unsigned long *)0x400FE73C))
-#define SYSCTL_SCGCEEPROM_R (*((volatile unsigned long *)0x400FE758))
-#define SYSCTL_SCGCWTIMER_R (*((volatile unsigned long *)0x400FE75C))
-#define SYSCTL_DCGCWD_R (*((volatile unsigned long *)0x400FE800))
-#define SYSCTL_DCGCTIMER_R (*((volatile unsigned long *)0x400FE804))
-#define SYSCTL_DCGCGPIO_R (*((volatile unsigned long *)0x400FE808))
-#define SYSCTL_DCGCDMA_R (*((volatile unsigned long *)0x400FE80C))
-#define SYSCTL_DCGCHIB_R (*((volatile unsigned long *)0x400FE814))
-#define SYSCTL_DCGCUART_R (*((volatile unsigned long *)0x400FE818))
-#define SYSCTL_DCGCSSI_R (*((volatile unsigned long *)0x400FE81C))
-#define SYSCTL_DCGCI2C_R (*((volatile unsigned long *)0x400FE820))
-#define SYSCTL_DCGCUSB_R (*((volatile unsigned long *)0x400FE828))
-#define SYSCTL_DCGCCAN_R (*((volatile unsigned long *)0x400FE834))
-#define SYSCTL_DCGCADC_R (*((volatile unsigned long *)0x400FE838))
-#define SYSCTL_DCGCACMP_R (*((volatile unsigned long *)0x400FE83C))
-#define SYSCTL_DCGCEEPROM_R (*((volatile unsigned long *)0x400FE858))
-#define SYSCTL_DCGCWTIMER_R (*((volatile unsigned long *)0x400FE85C))
-#define SYSCTL_PCWD_R (*((volatile unsigned long *)0x400FE900))
-#define SYSCTL_PCTIMER_R (*((volatile unsigned long *)0x400FE904))
-#define SYSCTL_PCGPIO_R (*((volatile unsigned long *)0x400FE908))
-#define SYSCTL_PCDMA_R (*((volatile unsigned long *)0x400FE90C))
-#define SYSCTL_PCHIB_R (*((volatile unsigned long *)0x400FE914))
-#define SYSCTL_PCUART_R (*((volatile unsigned long *)0x400FE918))
-#define SYSCTL_PCSSI_R (*((volatile unsigned long *)0x400FE91C))
-#define SYSCTL_PCI2C_R (*((volatile unsigned long *)0x400FE920))
-#define SYSCTL_PCUSB_R (*((volatile unsigned long *)0x400FE928))
-#define SYSCTL_PCCAN_R (*((volatile unsigned long *)0x400FE934))
-#define SYSCTL_PCADC_R (*((volatile unsigned long *)0x400FE938))
-#define SYSCTL_PCACMP_R (*((volatile unsigned long *)0x400FE93C))
-#define SYSCTL_PCEEPROM_R (*((volatile unsigned long *)0x400FE958))
-#define SYSCTL_PCWTIMER_R (*((volatile unsigned long *)0x400FE95C))
-#define SYSCTL_PRWD_R (*((volatile unsigned long *)0x400FEA00))
-#define SYSCTL_PRTIMER_R (*((volatile unsigned long *)0x400FEA04))
-#define SYSCTL_PRGPIO_R (*((volatile unsigned long *)0x400FEA08))
-#define SYSCTL_PRDMA_R (*((volatile unsigned long *)0x400FEA0C))
-#define SYSCTL_PRHIB_R (*((volatile unsigned long *)0x400FEA14))
-#define SYSCTL_PRUART_R (*((volatile unsigned long *)0x400FEA18))
-#define SYSCTL_PRSSI_R (*((volatile unsigned long *)0x400FEA1C))
-#define SYSCTL_PRI2C_R (*((volatile unsigned long *)0x400FEA20))
-#define SYSCTL_PRUSB_R (*((volatile unsigned long *)0x400FEA28))
-#define SYSCTL_PRCAN_R (*((volatile unsigned long *)0x400FEA34))
-#define SYSCTL_PRADC_R (*((volatile unsigned long *)0x400FEA38))
-#define SYSCTL_PRACMP_R (*((volatile unsigned long *)0x400FEA3C))
-#define SYSCTL_PREEPROM_R (*((volatile unsigned long *)0x400FEA58))
-#define SYSCTL_PRWTIMER_R (*((volatile unsigned long *)0x400FEA5C))
-
-//*****************************************************************************
-//
-// Micro Direct Memory Access registers (UDMA)
-//
-//*****************************************************************************
-#define UDMA_STAT_R (*((volatile unsigned long *)0x400FF000))
-#define UDMA_CFG_R (*((volatile unsigned long *)0x400FF004))
-#define UDMA_CTLBASE_R (*((volatile unsigned long *)0x400FF008))
-#define UDMA_ALTBASE_R (*((volatile unsigned long *)0x400FF00C))
-#define UDMA_WAITSTAT_R (*((volatile unsigned long *)0x400FF010))
-#define UDMA_SWREQ_R (*((volatile unsigned long *)0x400FF014))
-#define UDMA_USEBURSTSET_R (*((volatile unsigned long *)0x400FF018))
-#define UDMA_USEBURSTCLR_R (*((volatile unsigned long *)0x400FF01C))
-#define UDMA_REQMASKSET_R (*((volatile unsigned long *)0x400FF020))
-#define UDMA_REQMASKCLR_R (*((volatile unsigned long *)0x400FF024))
-#define UDMA_ENASET_R (*((volatile unsigned long *)0x400FF028))
-#define UDMA_ENACLR_R (*((volatile unsigned long *)0x400FF02C))
-#define UDMA_ALTSET_R (*((volatile unsigned long *)0x400FF030))
-#define UDMA_ALTCLR_R (*((volatile unsigned long *)0x400FF034))
-#define UDMA_PRIOSET_R (*((volatile unsigned long *)0x400FF038))
-#define UDMA_PRIOCLR_R (*((volatile unsigned long *)0x400FF03C))
-#define UDMA_ERRCLR_R (*((volatile unsigned long *)0x400FF04C))
-#define UDMA_CHASGN_R (*((volatile unsigned long *)0x400FF500))
-#define UDMA_CHIS_R (*((volatile unsigned long *)0x400FF504))
-#define UDMA_CHMAP0_R (*((volatile unsigned long *)0x400FF510))
-#define UDMA_CHMAP1_R (*((volatile unsigned long *)0x400FF514))
-#define UDMA_CHMAP2_R (*((volatile unsigned long *)0x400FF518))
-#define UDMA_CHMAP3_R (*((volatile unsigned long *)0x400FF51C))
-
-//*****************************************************************************
-//
-// Micro Direct Memory Access (uDMA) offsets (UDMA)
-//
-//*****************************************************************************
-#define UDMA_SRCENDP 0x00000000 // DMA Channel Source Address End
- // Pointer
-#define UDMA_DSTENDP 0x00000004 // DMA Channel Destination Address
- // End Pointer
-#define UDMA_CHCTL 0x00000008 // DMA Channel Control Word
-
-//*****************************************************************************
-//
-// NVIC registers (NVIC)
-//
-//*****************************************************************************
-#define NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004))
-#define NVIC_ACTLR_R (*((volatile unsigned long *)0xE000E008))
-#define NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010))
-#define NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014))
-#define NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018))
-#define NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C))
-#define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100))
-#define NVIC_EN1_R (*((volatile unsigned long *)0xE000E104))
-#define NVIC_EN2_R (*((volatile unsigned long *)0xE000E108))
-#define NVIC_EN3_R (*((volatile unsigned long *)0xE000E10C))
-#define NVIC_EN4_R (*((volatile unsigned long *)0xE000E110))
-#define NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180))
-#define NVIC_DIS1_R (*((volatile unsigned long *)0xE000E184))
-#define NVIC_DIS2_R (*((volatile unsigned long *)0xE000E188))
-#define NVIC_DIS3_R (*((volatile unsigned long *)0xE000E18C))
-#define NVIC_DIS4_R (*((volatile unsigned long *)0xE000E190))
-#define NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200))
-#define NVIC_PEND1_R (*((volatile unsigned long *)0xE000E204))
-#define NVIC_PEND2_R (*((volatile unsigned long *)0xE000E208))
-#define NVIC_PEND3_R (*((volatile unsigned long *)0xE000E20C))
-#define NVIC_PEND4_R (*((volatile unsigned long *)0xE000E210))
-#define NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280))
-#define NVIC_UNPEND1_R (*((volatile unsigned long *)0xE000E284))
-#define NVIC_UNPEND2_R (*((volatile unsigned long *)0xE000E288))
-#define NVIC_UNPEND3_R (*((volatile unsigned long *)0xE000E28C))
-#define NVIC_UNPEND4_R (*((volatile unsigned long *)0xE000E290))
-#define NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300))
-#define NVIC_ACTIVE1_R (*((volatile unsigned long *)0xE000E304))
-#define NVIC_ACTIVE2_R (*((volatile unsigned long *)0xE000E308))
-#define NVIC_ACTIVE3_R (*((volatile unsigned long *)0xE000E30C))
-#define NVIC_ACTIVE4_R (*((volatile unsigned long *)0xE000E310))
-#define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400))
-#define NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404))
-#define NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408))
-#define NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C))
-#define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410))
-#define NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414))
-#define NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418))
-#define NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C))
-#define NVIC_PRI8_R (*((volatile unsigned long *)0xE000E420))
-#define NVIC_PRI9_R (*((volatile unsigned long *)0xE000E424))
-#define NVIC_PRI10_R (*((volatile unsigned long *)0xE000E428))
-#define NVIC_PRI11_R (*((volatile unsigned long *)0xE000E42C))
-#define NVIC_PRI12_R (*((volatile unsigned long *)0xE000E430))
-#define NVIC_PRI13_R (*((volatile unsigned long *)0xE000E434))
-#define NVIC_PRI14_R (*((volatile unsigned long *)0xE000E438))
-#define NVIC_PRI15_R (*((volatile unsigned long *)0xE000E43C))
-#define NVIC_PRI16_R (*((volatile unsigned long *)0xE000E440))
-#define NVIC_PRI17_R (*((volatile unsigned long *)0xE000E444))
-#define NVIC_PRI18_R (*((volatile unsigned long *)0xE000E448))
-#define NVIC_PRI19_R (*((volatile unsigned long *)0xE000E44C))
-#define NVIC_PRI20_R (*((volatile unsigned long *)0xE000E450))
-#define NVIC_PRI21_R (*((volatile unsigned long *)0xE000E454))
-#define NVIC_PRI22_R (*((volatile unsigned long *)0xE000E458))
-#define NVIC_PRI23_R (*((volatile unsigned long *)0xE000E45C))
-#define NVIC_PRI24_R (*((volatile unsigned long *)0xE000E460))
-#define NVIC_PRI25_R (*((volatile unsigned long *)0xE000E464))
-#define NVIC_PRI26_R (*((volatile unsigned long *)0xE000E468))
-#define NVIC_PRI27_R (*((volatile unsigned long *)0xE000E46C))
-#define NVIC_PRI28_R (*((volatile unsigned long *)0xE000E470))
-#define NVIC_PRI29_R (*((volatile unsigned long *)0xE000E474))
-#define NVIC_PRI30_R (*((volatile unsigned long *)0xE000E478))
-#define NVIC_PRI31_R (*((volatile unsigned long *)0xE000E47C))
-#define NVIC_PRI32_R (*((volatile unsigned long *)0xE000E480))
-#define NVIC_PRI33_R (*((volatile unsigned long *)0xE000E484))
-#define NVIC_PRI34_R (*((volatile unsigned long *)0xE000E488))
-#define NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00))
-#define NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04))
-#define NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08))
-#define NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C))
-#define NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10))
-#define NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14))
-#define NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18))
-#define NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C))
-#define NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20))
-#define NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24))
-#define NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28))
-#define NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C))
-#define NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30))
-#define NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34))
-#define NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38))
-#define NVIC_CPAC_R (*((volatile unsigned long *)0xE000ED88))
-#define NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90))
-#define NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94))
-#define NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98))
-#define NVIC_MPU_BASE_R (*((volatile unsigned long *)0xE000ED9C))
-#define NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0))
-#define NVIC_MPU_BASE1_R (*((volatile unsigned long *)0xE000EDA4))
-#define NVIC_MPU_ATTR1_R (*((volatile unsigned long *)0xE000EDA8))
-#define NVIC_MPU_BASE2_R (*((volatile unsigned long *)0xE000EDAC))
-#define NVIC_MPU_ATTR2_R (*((volatile unsigned long *)0xE000EDB0))
-#define NVIC_MPU_BASE3_R (*((volatile unsigned long *)0xE000EDB4))
-#define NVIC_MPU_ATTR3_R (*((volatile unsigned long *)0xE000EDB8))
-#define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0))
-#define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4))
-#define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8))
-#define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC))
-#define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00))
-#define NVIC_FPCC_R (*((volatile unsigned long *)0xE000EF34))
-#define NVIC_FPCA_R (*((volatile unsigned long *)0xE000EF38))
-#define NVIC_FPDSC_R (*((volatile unsigned long *)0xE000EF3C))
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_LOAD register.
-//
-//*****************************************************************************
-#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
-#define WDT_LOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_VALUE register.
-//
-//*****************************************************************************
-#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
-#define WDT_VALUE_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_CTL register.
-//
-//*****************************************************************************
-#define WDT_CTL_WRC 0x80000000 // Write Complete
-#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
-#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
-#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_ICR register.
-//
-//*****************************************************************************
-#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
-#define WDT_ICR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_RIS register.
-//
-//*****************************************************************************
-#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_MIS register.
-//
-//*****************************************************************************
-#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_TEST register.
-//
-//*****************************************************************************
-#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the WDT_O_LOCK register.
-//
-//*****************************************************************************
-#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
-#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
-#define WDT_LOCK_LOCKED 0x00000001 // Locked
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_IM register.
-//
-//*****************************************************************************
-#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
-#define GPIO_IM_GPIO_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_RIS register.
-//
-//*****************************************************************************
-#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
-#define GPIO_RIS_GPIO_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_MIS register.
-//
-//*****************************************************************************
-#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
-#define GPIO_MIS_GPIO_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_ICR register.
-//
-//*****************************************************************************
-#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
-#define GPIO_ICR_GPIO_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_LOCK register.
-//
-//*****************************************************************************
-#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
-#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
- // and may be modified
-#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
- // and may not be modified
-#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_O_SI register.
-//
-//*****************************************************************************
-#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_PCTL register for
-// port A.
-//
-//*****************************************************************************
-#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask
-#define GPIO_PCTL_PA7_I2C1SDA 0x30000000 // I2C1SDA on PA7
-#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask
-#define GPIO_PCTL_PA6_I2C1SCL 0x03000000 // I2C1SCL on PA6
-#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 mask
-#define GPIO_PCTL_PA5_SSI0TX 0x00200000 // SSI0TX on PA5
-#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 mask
-#define GPIO_PCTL_PA4_SSI0RX 0x00020000 // SSI0RX on PA4
-#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 mask
-#define GPIO_PCTL_PA3_SSI0FSS 0x00002000 // SSI0FSS on PA3
-#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 mask
-#define GPIO_PCTL_PA2_SSI0CLK 0x00000200 // SSI0CLK on PA2
-#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 mask
-#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1
-#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask
-#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_PCTL register for
-// port B.
-//
-//*****************************************************************************
-#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 mask
-#define GPIO_PCTL_PB7_SSI2TX 0x20000000 // SSI2TX on PB7
-#define GPIO_PCTL_PB7_T0CCP1 0x70000000 // T0CCP1 on PB7
-#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 mask
-#define GPIO_PCTL_PB6_SSI2RX 0x02000000 // SSI2RX on PB6
-#define GPIO_PCTL_PB6_T0CCP0 0x07000000 // T0CCP0 on PB6
-#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 mask
-#define GPIO_PCTL_PB5_SSI2FSS 0x00200000 // SSI2FSS on PB5
-#define GPIO_PCTL_PB5_T1CCP1 0x00700000 // T1CCP1 on PB5
-#define GPIO_PCTL_PB5_CAN0TX 0x00800000 // CAN0TX on PB5
-#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 mask
-#define GPIO_PCTL_PB4_SSI2CLK 0x00020000 // SSI2CLK on PB4
-#define GPIO_PCTL_PB4_T1CCP0 0x00070000 // T1CCP0 on PB4
-#define GPIO_PCTL_PB4_CAN0RX 0x00080000 // CAN0RX on PB4
-#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 mask
-#define GPIO_PCTL_PB3_I2C0SDA 0x00003000 // I2C0SDA on PB3
-#define GPIO_PCTL_PB3_T3CCP1 0x00007000 // T3CCP1 on PB3
-#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 mask
-#define GPIO_PCTL_PB2_I2C0SCL 0x00000300 // I2C0SCL on PB2
-#define GPIO_PCTL_PB2_T3CCP0 0x00000700 // T3CCP0 on PB2
-#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 mask
-#define GPIO_PCTL_PB1_U1TX 0x00000010 // U1TX on PB1
-#define GPIO_PCTL_PB1_T2CCP1 0x00000070 // T2CCP1 on PB1
-#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask
-#define GPIO_PCTL_PB0_U1RX 0x00000001 // U1RX on PB0
-#define GPIO_PCTL_PB0_T2CCP0 0x00000007 // T2CCP0 on PB0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_PCTL register for
-// port C.
-//
-//*****************************************************************************
-#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask
-#define GPIO_PCTL_PC7_U3TX 0x10000000 // U3TX on PC7
-#define GPIO_PCTL_PC7_WT1CCP1 0x70000000 // WT1CCP1 on PC7
-#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask
-#define GPIO_PCTL_PC6_U3RX 0x01000000 // U3RX on PC6
-#define GPIO_PCTL_PC6_WT1CCP0 0x07000000 // WT1CCP0 on PC6
-#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 mask
-#define GPIO_PCTL_PC5_U4TX 0x00100000 // U4TX on PC5
-#define GPIO_PCTL_PC5_U1TX 0x00200000 // U1TX on PC5
-#define GPIO_PCTL_PC5_WT0CCP1 0x00700000 // WT0CCP1 on PC5
-#define GPIO_PCTL_PC5_U1CTS 0x00800000 // U1CTS on PC5
-#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 mask
-#define GPIO_PCTL_PC4_U4RX 0x00010000 // U4RX on PC4
-#define GPIO_PCTL_PC4_U1RX 0x00020000 // U1RX on PC4
-#define GPIO_PCTL_PC4_WT0CCP0 0x00070000 // WT0CCP0 on PC4
-#define GPIO_PCTL_PC4_U1RTS 0x00080000 // U1RTS on PC4
-#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 mask
-#define GPIO_PCTL_PC3_TDO 0x00001000 // TDO on PC3
-#define GPIO_PCTL_PC3_T5CCP1 0x00007000 // T5CCP1 on PC3
-#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 mask
-#define GPIO_PCTL_PC2_TDI 0x00000100 // TDI on PC2
-#define GPIO_PCTL_PC2_T5CCP0 0x00000700 // T5CCP0 on PC2
-#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 mask
-#define GPIO_PCTL_PC1_TMS 0x00000010 // TMS on PC1
-#define GPIO_PCTL_PC1_T4CCP1 0x00000070 // T4CCP1 on PC1
-#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask
-#define GPIO_PCTL_PC0_TCK 0x00000001 // TCK on PC0
-#define GPIO_PCTL_PC0_T4CCP0 0x00000007 // T4CCP0 on PC0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_PCTL register for
-// port D.
-//
-//*****************************************************************************
-#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask
-#define GPIO_PCTL_PD7_U2TX 0x10000000 // U2TX on PD7
-#define GPIO_PCTL_PD7_WT5CCP1 0x70000000 // WT5CCP1 on PD7
-#define GPIO_PCTL_PD7_NMI 0x80000000 // NMI on PD7
-#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask
-#define GPIO_PCTL_PD6_U2RX 0x01000000 // U2RX on PD6
-#define GPIO_PCTL_PD6_WT5CCP0 0x07000000 // WT5CCP0 on PD6
-#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 mask
-#define GPIO_PCTL_PD5_U6TX 0x00100000 // U6TX on PD5
-#define GPIO_PCTL_PD5_WT4CCP1 0x00700000 // WT4CCP1 on PD5
-#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 mask
-#define GPIO_PCTL_PD4_U6RX 0x00010000 // U6RX on PD4
-#define GPIO_PCTL_PD4_WT4CCP0 0x00070000 // WT4CCP0 on PD4
-#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 mask
-#define GPIO_PCTL_PD3_SSI3TX 0x00001000 // SSI3TX on PD3
-#define GPIO_PCTL_PD3_SSI1TX 0x00002000 // SSI1TX on PD3
-#define GPIO_PCTL_PD3_WT3CCP1 0x00007000 // WT3CCP1 on PD3
-#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 mask
-#define GPIO_PCTL_PD2_SSI3RX 0x00000100 // SSI3RX on PD2
-#define GPIO_PCTL_PD2_SSI1RX 0x00000200 // SSI1RX on PD2
-#define GPIO_PCTL_PD2_WT3CCP0 0x00000700 // WT3CCP0 on PD2
-#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 mask
-#define GPIO_PCTL_PD1_SSI3FSS 0x00000010 // SSI3FSS on PD1
-#define GPIO_PCTL_PD1_SSI1FSS 0x00000020 // SSI1FSS on PD1
-#define GPIO_PCTL_PD1_I2C3SDA 0x00000030 // I2C3SDA on PD1
-#define GPIO_PCTL_PD1_WT2CCP1 0x00000070 // WT2CCP1 on PD1
-#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask
-#define GPIO_PCTL_PD0_SSI3CLK 0x00000001 // SSI3CLK on PD0
-#define GPIO_PCTL_PD0_SSI1CLK 0x00000002 // SSI1CLK on PD0
-#define GPIO_PCTL_PD0_I2C3SCL 0x00000003 // I2C3SCL on PD0
-#define GPIO_PCTL_PD0_WT2CCP0 0x00000007 // WT2CCP0 on PD0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_PCTL register for
-// port E.
-//
-//*****************************************************************************
-#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 mask
-#define GPIO_PCTL_PE5_U5TX 0x00100000 // U5TX on PE5
-#define GPIO_PCTL_PE5_I2C2SDA 0x00300000 // I2C2SDA on PE5
-#define GPIO_PCTL_PE5_CAN0TX 0x00800000 // CAN0TX on PE5
-#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 mask
-#define GPIO_PCTL_PE4_U5RX 0x00010000 // U5RX on PE4
-#define GPIO_PCTL_PE4_I2C2SCL 0x00030000 // I2C2SCL on PE4
-#define GPIO_PCTL_PE4_CAN0RX 0x00080000 // CAN0RX on PE4
-#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 mask
-#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 mask
-#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 mask
-#define GPIO_PCTL_PE1_U7TX 0x00000010 // U7TX on PE1
-#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask
-#define GPIO_PCTL_PE0_U7RX 0x00000001 // U7RX on PE0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the GPIO_PCTL register for
-// port F.
-//
-//*****************************************************************************
-#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 mask
-#define GPIO_PCTL_PF4_T2CCP0 0x00070000 // T2CCP0 on PF4
-#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 mask
-#define GPIO_PCTL_PF3_SSI1FSS 0x00002000 // SSI1FSS on PF3
-#define GPIO_PCTL_PF3_CAN0TX 0x00003000 // CAN0TX on PF3
-#define GPIO_PCTL_PF3_T1CCP1 0x00007000 // T1CCP1 on PF3
-#define GPIO_PCTL_PF3_TRCLK 0x0000E000 // TRCLK on PF3
-#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 mask
-#define GPIO_PCTL_PF2_SSI1CLK 0x00000200 // SSI1CLK on PF2
-#define GPIO_PCTL_PF2_T1CCP0 0x00000700 // T1CCP0 on PF2
-#define GPIO_PCTL_PF2_TRD0 0x00000E00 // TRD0 on PF2
-#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 mask
-#define GPIO_PCTL_PF1_U1CTS 0x00000010 // U1CTS on PF1
-#define GPIO_PCTL_PF1_SSI1TX 0x00000020 // SSI1TX on PF1
-#define GPIO_PCTL_PF1_T0CCP1 0x00000070 // T0CCP1 on PF1
-#define GPIO_PCTL_PF1_C1O 0x00000090 // C1O on PF1
-#define GPIO_PCTL_PF1_TRD1 0x000000E0 // TRD1 on PF1
-#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask
-#define GPIO_PCTL_PF0_U1RTS 0x00000001 // U1RTS on PF0
-#define GPIO_PCTL_PF0_SSI1RX 0x00000002 // SSI1RX on PF0
-#define GPIO_PCTL_PF0_CAN0RX 0x00000003 // CAN0RX on PF0
-#define GPIO_PCTL_PF0_T0CCP0 0x00000007 // T0CCP0 on PF0
-#define GPIO_PCTL_PF0_NMI 0x00000008 // NMI on PF0
-#define GPIO_PCTL_PF0_C0O 0x00000009 // C0O on PF0
-#define GPIO_PCTL_PF0_TRD2 0x0000000E // TRD2 on PF0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_CR0 register.
-//
-//*****************************************************************************
-#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
-#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
-#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
-#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
-#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
-#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
- // Serial Frame Format
-#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
-#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
-#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
-#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
-#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
-#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
-#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
-#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
-#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
-#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
-#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
-#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
-#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
-#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
-#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
-#define SSI_CR0_SCR_S 8
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_CR1 register.
-//
-//*****************************************************************************
-#define SSI_CR1_EOT 0x00000010 // End of Transmission
-#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
-#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
-#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
- // Enable
-#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_DR register.
-//
-//*****************************************************************************
-#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
-#define SSI_DR_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_SR register.
-//
-//*****************************************************************************
-#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
-#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
-#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
-#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
-#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_CPSR register.
-//
-//*****************************************************************************
-#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
-#define SSI_CPSR_CPSDVSR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_IM register.
-//
-//*****************************************************************************
-#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
-#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
-#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
- // Mask
-#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
- // Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_RIS register.
-//
-//*****************************************************************************
-#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
- // Status
-#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
- // Status
-#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
- // Interrupt Status
-#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
- // Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_MIS register.
-//
-//*****************************************************************************
-#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
- // Interrupt Status
-#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
- // Interrupt Status
-#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
- // Interrupt Status
-#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
- // Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_ICR register.
-//
-//*****************************************************************************
-#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
- // Clear
-#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
- // Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_DMACTL register.
-//
-//*****************************************************************************
-#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
-#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SSI_O_CC register.
-//
-//*****************************************************************************
-#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
-#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
- // PLL bypass is in effect) or the
- // PLL output (default)
-#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_DR register.
-//
-//*****************************************************************************
-#define UART_DR_OE 0x00000800 // UART Overrun Error
-#define UART_DR_BE 0x00000400 // UART Break Error
-#define UART_DR_PE 0x00000200 // UART Parity Error
-#define UART_DR_FE 0x00000100 // UART Framing Error
-#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
-#define UART_DR_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_RSR register.
-//
-//*****************************************************************************
-#define UART_RSR_OE 0x00000008 // UART Overrun Error
-#define UART_RSR_BE 0x00000004 // UART Break Error
-#define UART_RSR_PE 0x00000002 // UART Parity Error
-#define UART_RSR_FE 0x00000001 // UART Framing Error
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_ECR register.
-//
-//*****************************************************************************
-#define UART_ECR_DATA_M 0x000000FF // Error Clear
-#define UART_ECR_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_FR register.
-//
-//*****************************************************************************
-#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
-#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
-#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
-#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
-#define UART_FR_BUSY 0x00000008 // UART Busy
-#define UART_FR_CTS 0x00000001 // Clear To Send
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_ILPR register.
-//
-//*****************************************************************************
-#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
-#define UART_ILPR_ILPDVSR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_IBRD register.
-//
-//*****************************************************************************
-#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
-#define UART_IBRD_DIVINT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_FBRD register.
-//
-//*****************************************************************************
-#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
-#define UART_FBRD_DIVFRAC_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_LCRH register.
-//
-//*****************************************************************************
-#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
-#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
-#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
-#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
-#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
-#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
-#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
-#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
-#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
-#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
-#define UART_LCRH_BRK 0x00000001 // UART Send Break
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_CTL register.
-//
-//*****************************************************************************
-#define UART_CTL_RXE 0x00000200 // UART Receive Enable
-#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
-#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
-#define UART_CTL_LIN 0x00000040 // LIN Mode Enable
-#define UART_CTL_HSE 0x00000020 // High-Speed Enable
-#define UART_CTL_EOT 0x00000010 // End of Transmission
-#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
-#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
-#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
-#define UART_CTL_UARTEN 0x00000001 // UART Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_IFLS register.
-//
-//*****************************************************************************
-#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
- // Level Select
-#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
-#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
-#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
-#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
-#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
-#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
- // Level Select
-#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
-#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
-#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
-#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
-#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_IM register.
-//
-//*****************************************************************************
-#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
-#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
-#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
- // Mask
-#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
-#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
- // Mask
-#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
-#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
-#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
- // Mask
-#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
- // Mask
-#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
-#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
-#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
- // Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_RIS register.
-//
-//*****************************************************************************
-#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
- // Status
-#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
- // Status
-#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
- // Interrupt Status
-#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
-#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
- // Status
-#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
- // Status
-#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
- // Status
-#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
- // Status
-#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
- // Interrupt Status
-#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
- // Status
-#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
- // Status
-#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
- // Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_MIS register.
-//
-//*****************************************************************************
-#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
- // Status
-#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
- // Status
-#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
- // Interrupt Status
-#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
- // Status
-#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
- // Interrupt Status
-#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
- // Interrupt Status
-#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
- // Interrupt Status
-#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
- // Interrupt Status
-#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
- // Interrupt Status
-#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
- // Status
-#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
- // Status
-#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
- // Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_ICR register.
-//
-//*****************************************************************************
-#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
-#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
-#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt
- // Clear
-#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
-#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
-#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
-#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
-#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
-#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
-#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
-#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
-#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
- // Interrupt Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_DMACTL register.
-//
-//*****************************************************************************
-#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
-#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
-#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_LCTL register.
-//
-//*****************************************************************************
-#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length
-#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits
- // (default)
-#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits
-#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits
-#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits
-#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_LSS register.
-//
-//*****************************************************************************
-#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
-#define UART_LSS_TSS_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_LTIM register.
-//
-//*****************************************************************************
-#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
-#define UART_LTIM_TIMER_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_9BITADDR
-// register.
-//
-//*****************************************************************************
-#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
-#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
-#define UART_9BITADDR_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_9BITAMASK
-// register.
-//
-//*****************************************************************************
-#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
-#define UART_9BITAMASK_MASK_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_PP register.
-//
-//*****************************************************************************
-#define UART_PP_NB 0x00000002 // 9-Bit Support
-#define UART_PP_SC 0x00000001 // Smart Card Support
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UART_O_CC register.
-//
-//*****************************************************************************
-#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
-#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default)
-#define UART_CC_CS_PIOSC 0x00000005 // PIOSC
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MSA register.
-//
-//*****************************************************************************
-#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
-#define I2C_MSA_RS 0x00000001 // Receive not send
-#define I2C_MSA_SA_S 1
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SOAR register.
-//
-//*****************************************************************************
-#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
-#define I2C_SOAR_OAR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SCSR register.
-//
-//*****************************************************************************
-#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
-#define I2C_SCSR_FBR 0x00000004 // First Byte Received
-#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
-#define I2C_SCSR_DA 0x00000001 // Device Active
-#define I2C_SCSR_RREQ 0x00000001 // Receive Request
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MCS register.
-//
-//*****************************************************************************
-#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
-#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
-#define I2C_MCS_IDLE 0x00000020 // I2C Idle
-#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
-#define I2C_MCS_HS 0x00000010 // High-Speed Enable
-#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
-#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
-#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
-#define I2C_MCS_STOP 0x00000004 // Generate STOP
-#define I2C_MCS_ERROR 0x00000002 // Error
-#define I2C_MCS_START 0x00000002 // Generate START
-#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
-#define I2C_MCS_BUSY 0x00000001 // I2C Busy
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SDR register.
-//
-//*****************************************************************************
-#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
-#define I2C_SDR_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MDR register.
-//
-//*****************************************************************************
-#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
-#define I2C_MDR_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MTPR register.
-//
-//*****************************************************************************
-#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
-#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
-#define I2C_MTPR_TPR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SIMR register.
-//
-//*****************************************************************************
-#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
-#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
-#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SRIS register.
-//
-//*****************************************************************************
-#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
- // Status
-#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
- // Status
-#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MIMR register.
-//
-//*****************************************************************************
-#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
-#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MRIS register.
-//
-//*****************************************************************************
-#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
- // Status
-#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SMIS register.
-//
-//*****************************************************************************
-#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
- // Status
-#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
- // Status
-#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SICR register.
-//
-//*****************************************************************************
-#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
-#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
-#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MMIS register.
-//
-//*****************************************************************************
-#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
- // Status
-#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MICR register.
-//
-//*****************************************************************************
-#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
-#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SOAR2 register.
-//
-//*****************************************************************************
-#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
-#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
-#define I2C_SOAR2_OAR2_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MCR register.
-//
-//*****************************************************************************
-#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
-#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
-#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_SACKCTL register.
-//
-//*****************************************************************************
-#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
-#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
-//
-//*****************************************************************************
-#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
-#define I2C_MCLKOCNT_CNTL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_MBMON register.
-//
-//*****************************************************************************
-#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
-#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_PP register.
-//
-//*****************************************************************************
-#define I2C_PP_HS 0x00000001 // High-Speed Capable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the I2C_O_PC register.
-//
-//*****************************************************************************
-#define I2C_PC_HS 0x00000001 // High-Speed Capable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_CFG register.
-//
-//*****************************************************************************
-#define TIMER_CFG_M 0x00000007 // GPTM Configuration
-#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
-#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
- // counter configuration
-#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
- // function is controlled by bits
- // 1:0 of GPTMTAMR and GPTMTBMR
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAMR register.
-//
-//*****************************************************************************
-#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
- // Operation
-#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
- // Update
-#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
- // Enable
-#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
-#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
-#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
-#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
- // Enable
-#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
-#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
- // Select
-#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
-#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
-#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
-#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
-#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBMR register.
-//
-//*****************************************************************************
-#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
- // Operation
-#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
- // Update
-#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
- // Enable
-#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
-#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
-#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
-#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
- // Enable
-#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
-#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
- // Select
-#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
-#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
-#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
-#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
-#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_CTL register.
-//
-//*****************************************************************************
-#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
-#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
- // Enable
-#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
-#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
-#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
-#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
-#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
-#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
-#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
-#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
- // Enable
-#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable
-#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
-#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
-#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
-#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
-#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
-#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_SYNC register.
-//
-//*****************************************************************************
-#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer
- // 5
-#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not
- // affected
-#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of
- // GPTM 32/64-Bit Timer 5 is
- // triggered
-#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of
- // GPTM 32/64-Bit Timer 5 is
- // triggered
-#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A
- // and Timer B of GPTM 32/64-Bit
- // Timer 5 is triggered
-#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer
- // 4
-#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not
- // affected
-#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of
- // GPTM 32/64-Bit Timer 4 is
- // triggered
-#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of
- // GPTM 32/64-Bit Timer 4 is
- // triggered
-#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A
- // and Timer B of GPTM 32/64-Bit
- // Timer 4 is triggered
-#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer
- // 3
-#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not
- // affected
-#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of
- // GPTM 32/64-Bit Timer 3 is
- // triggered
-#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of
- // GPTM 32/64-Bit Timer 3 is
- // triggered
-#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A
- // and Timer B of GPTM 32/64-Bit
- // Timer 3 is triggered
-#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer
- // 2
-#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not
- // affected
-#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of
- // GPTM 32/64-Bit Timer 2 is
- // triggered
-#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of
- // GPTM 32/64-Bit Timer 2 is
- // triggered
-#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A
- // and Timer B of GPTM 32/64-Bit
- // Timer 2 is triggered
-#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer
- // 1
-#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not
- // affected
-#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of
- // GPTM 32/64-Bit Timer 1 is
- // triggered
-#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of
- // GPTM 32/64-Bit Timer 1 is
- // triggered
-#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A
- // and Timer B of GPTM 32/64-Bit
- // Timer 1 is triggered
-#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer
- // 0
-#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not
- // affected
-#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of
- // GPTM 32/64-Bit Timer 0 is
- // triggered
-#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of
- // GPTM 32/64-Bit Timer 0 is
- // triggered
-#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A
- // and Timer B of GPTM 32/64-Bit
- // Timer 0 is triggered
-#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer
- // 5
-#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not
- // affected
-#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
- // GPTM 16/32-Bit Timer 5 is
- // triggered
-#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
- // GPTM 16/32-Bit Timer 5 is
- // triggered
-#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
- // and Timer B of GPTM 16/32-Bit
- // Timer 5 is triggered
-#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer
- // 4
-#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not
- // affected
-#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
- // GPTM 16/32-Bit Timer 4 is
- // triggered
-#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
- // GPTM 16/32-Bit Timer 4 is
- // triggered
-#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
- // and Timer B of GPTM 16/32-Bit
- // Timer 4 is triggered
-#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer
- // 3
-#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not
- // affected
-#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
- // GPTM 16/32-Bit Timer 3 is
- // triggered
-#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
- // GPTM 16/32-Bit Timer 3 is
- // triggered
-#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
- // and Timer B of GPTM 16/32-Bit
- // Timer 3 is triggered
-#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer
- // 2
-#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not
- // affected
-#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
- // GPTM 16/32-Bit Timer 2 is
- // triggered
-#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
- // GPTM 16/32-Bit Timer 2 is
- // triggered
-#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
- // and Timer B of GPTM 16/32-Bit
- // Timer 2 is triggered
-#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer
- // 1
-#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not
- // affected
-#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
- // GPTM 16/32-Bit Timer 1 is
- // triggered
-#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
- // GPTM 16/32-Bit Timer 1 is
- // triggered
-#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
- // and Timer B of GPTM 16/32-Bit
- // Timer 1 is triggered
-#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer
- // 0
-#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not
- // affected
-#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
- // GPTM 16/32-Bit Timer 0 is
- // triggered
-#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
- // GPTM 16/32-Bit Timer 0 is
- // triggered
-#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
- // and Timer B of GPTM 16/32-Bit
- // Timer 0 is triggered
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_IMR register.
-//
-//*****************************************************************************
-#define TIMER_IMR_WUEIM 0x00010000 // GPTM Write Update Error
- // Interrupt Mask
-#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt
- // Mask
-#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event
- // Interrupt Mask
-#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match
- // Interrupt Mask
-#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
- // Mask
-#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt
- // Mask
-#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
-#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event
- // Interrupt Mask
-#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match
- // Interrupt Mask
-#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
- // Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_RIS register.
-//
-//*****************************************************************************
-#define TIMER_RIS_WUERIS 0x00010000 // GPTM Write Update Error Raw
- // Interrupt
-#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt
-#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event
- // Raw Interrupt
-#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match
- // Raw Interrupt
-#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
- // Interrupt
-#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt
-#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
-#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event
- // Raw Interrupt
-#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match
- // Raw Interrupt
-#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
- // Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_MIS register.
-//
-//*****************************************************************************
-#define TIMER_MIS_WUEMIS 0x00010000 // GPTM Write Update Error Masked
- // Interrupt
-#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked
- // Interrupt
-#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event
- // Masked Interrupt
-#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match
- // Masked Interrupt
-#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
- // Interrupt
-#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked
- // Interrupt
-#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
-#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event
- // Masked Interrupt
-#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match
- // Masked Interrupt
-#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
- // Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_ICR register.
-//
-//*****************************************************************************
-#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update
- // Error Interrupt Clear
-#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt
- // Clear
-#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event
- // Interrupt Clear
-#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match
- // Interrupt Clear
-#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
- // Clear
-#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt
- // Clear
-#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
-#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event
- // Interrupt Clear
-#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match
- // Interrupt Clear
-#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
- // Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAILR register.
-//
-//*****************************************************************************
-#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
- // Register
-#define TIMER_TAILR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBILR register.
-//
-//*****************************************************************************
-#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
- // Register
-#define TIMER_TBILR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAMATCHR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
-#define TIMER_TAMATCHR_TAMR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBMATCHR
-// register.
-//
-//*****************************************************************************
-#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
-#define TIMER_TBMATCHR_TBMR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAPR register.
-//
-//*****************************************************************************
-#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
-#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
-#define TIMER_TAPR_TAPSRH_S 8
-#define TIMER_TAPR_TAPSR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBPR register.
-//
-//*****************************************************************************
-#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
-#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
-#define TIMER_TBPR_TBPSRH_S 8
-#define TIMER_TBPR_TBPSR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAPMR register.
-//
-//*****************************************************************************
-#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
- // Byte
-#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
-#define TIMER_TAPMR_TAPSMRH_S 8
-#define TIMER_TAPMR_TAPSMR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBPMR register.
-//
-//*****************************************************************************
-#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
- // Byte
-#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
-#define TIMER_TBPMR_TBPSMRH_S 8
-#define TIMER_TBPMR_TBPSMR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAR register.
-//
-//*****************************************************************************
-#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
-#define TIMER_TAR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBR register.
-//
-//*****************************************************************************
-#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
-#define TIMER_TBR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAV register.
-//
-//*****************************************************************************
-#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
-#define TIMER_TAV_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBV register.
-//
-//*****************************************************************************
-#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
-#define TIMER_TBV_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_RTCPD register.
-//
-//*****************************************************************************
-#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
-#define TIMER_RTCPD_RTCPD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAPS register.
-//
-//*****************************************************************************
-#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
-#define TIMER_TAPS_PSS_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBPS register.
-//
-//*****************************************************************************
-#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
-#define TIMER_TBPS_PSS_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TAPV register.
-//
-//*****************************************************************************
-#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
-#define TIMER_TAPV_PSV_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_TBPV register.
-//
-//*****************************************************************************
-#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
-#define TIMER_TBPV_PSV_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the TIMER_O_PP register.
-//
-//*****************************************************************************
-#define TIMER_PP_SIZE_M 0x0000000F // Count Size
-#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
- // 16 bits each with an 8-bit
- // prescale counter
-#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
- // 32 bits each with a 16-bit
- // prescale counter
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_ACTSS register.
-//
-//*****************************************************************************
-#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable
-#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable
-#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable
-#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_RIS register.
-//
-//*****************************************************************************
-#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt
- // Status
-#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status
-#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status
-#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status
-#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_IM register.
-//
-//*****************************************************************************
-#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on
- // SS3
-#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on
- // SS2
-#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on
- // SS1
-#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on
- // SS0
-#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask
-#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask
-#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask
-#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_ISC register.
-//
-//*****************************************************************************
-#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt
- // Status on SS3
-#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt
- // Status on SS2
-#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt
- // Status on SS1
-#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt
- // Status on SS0
-#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear
-#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear
-#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear
-#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_OSTAT register.
-//
-//*****************************************************************************
-#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow
-#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow
-#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow
-#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_EMUX register.
-//
-//*****************************************************************************
-#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select
-#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default)
-#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
-#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1
-#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4)
-#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
-#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
-#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select
-#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default)
-#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
-#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1
-#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4)
-#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
-#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
-#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select
-#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default)
-#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
-#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1
-#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4)
-#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
-#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
-#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select
-#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default)
-#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
-#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1
-#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4)
-#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
-#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_USTAT register.
-//
-//*****************************************************************************
-#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow
-#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow
-#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow
-#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSPRI register.
-//
-//*****************************************************************************
-#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority
-#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
-#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
-#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
-#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
-#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority
-#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
-#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
-#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
-#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
-#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority
-#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
-#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
-#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
-#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
-#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority
-#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
-#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
-#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
-#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SPC register.
-//
-//*****************************************************************************
-#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference
-#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0
-#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5
-#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0
-#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5
-#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0
-#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5
-#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0
-#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5
-#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0
-#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5
-#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0
-#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5
-#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0
-#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5
-#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0
-#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_PSSI register.
-//
-//*****************************************************************************
-#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize
-#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait
-#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate
-#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate
-#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate
-#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SAC register.
-//
-//*****************************************************************************
-#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control
-#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
-#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
-#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
-#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
-#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
-#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
-#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCISC register.
-//
-//*****************************************************************************
-#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt
- // Status and Clear
-#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt
- // Status and Clear
-#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt
- // Status and Clear
-#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt
- // Status and Clear
-#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt
- // Status and Clear
-#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt
- // Status and Clear
-#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt
- // Status and Clear
-#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt
- // Status and Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
-//
-//*****************************************************************************
-#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select
-#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select
-#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select
-#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select
-#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select
-#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select
-#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select
-#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select
-#define ADC_SSMUX0_MUX7_S 28
-#define ADC_SSMUX0_MUX6_S 24
-#define ADC_SSMUX0_MUX5_S 20
-#define ADC_SSMUX0_MUX4_S 16
-#define ADC_SSMUX0_MUX3_S 12
-#define ADC_SSMUX0_MUX2_S 8
-#define ADC_SSMUX0_MUX1_S 4
-#define ADC_SSMUX0_MUX0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
-//
-//*****************************************************************************
-#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select
-#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable
-#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence
-#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select
-#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select
-#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable
-#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence
-#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select
-#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select
-#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable
-#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence
-#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select
-#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select
-#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable
-#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence
-#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select
-#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select
-#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable
-#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence
-#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select
-#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select
-#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable
-#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence
-#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select
-#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select
-#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable
-#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence
-#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select
-#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select
-#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable
-#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence
-#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
-//
-//*****************************************************************************
-#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data
-#define ADC_SSFIFO0_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
-//
-//*****************************************************************************
-#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full
-#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty
-#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer
-#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer
-#define ADC_SSFSTAT0_HPTR_S 4
-#define ADC_SSFSTAT0_TPTR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSOP0 register.
-//
-//*****************************************************************************
-#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator
- // Operation
-#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator
- // Operation
-#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator
- // Operation
-#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator
- // Operation
-#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator
- // Operation
-#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator
- // Operation
-#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator
- // Operation
-#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator
- // Operation
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSDC0 register.
-//
-//*****************************************************************************
-#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator
- // Select
-#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator
- // Select
-#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator
- // Select
-#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator
- // Select
-#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
- // Select
-#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
- // Select
-#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
- // Select
-#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
- // Select
-#define ADC_SSDC0_S6DCSEL_S 24
-#define ADC_SSDC0_S5DCSEL_S 20
-#define ADC_SSDC0_S4DCSEL_S 16
-#define ADC_SSDC0_S3DCSEL_S 12
-#define ADC_SSDC0_S2DCSEL_S 8
-#define ADC_SSDC0_S1DCSEL_S 4
-#define ADC_SSDC0_S0DCSEL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
-//
-//*****************************************************************************
-#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select
-#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select
-#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select
-#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select
-#define ADC_SSMUX1_MUX3_S 12
-#define ADC_SSMUX1_MUX2_S 8
-#define ADC_SSMUX1_MUX1_S 4
-#define ADC_SSMUX1_MUX0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
-//
-//*****************************************************************************
-#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select
-#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable
-#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence
-#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select
-#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select
-#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable
-#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence
-#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select
-#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select
-#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable
-#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence
-#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select
-#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select
-#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable
-#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence
-#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
-//
-//*****************************************************************************
-#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data
-#define ADC_SSFIFO1_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
-//
-//*****************************************************************************
-#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full
-#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty
-#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer
-#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer
-#define ADC_SSFSTAT1_HPTR_S 4
-#define ADC_SSFSTAT1_TPTR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSOP1 register.
-//
-//*****************************************************************************
-#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator
- // Operation
-#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator
- // Operation
-#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator
- // Operation
-#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator
- // Operation
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSDC1 register.
-//
-//*****************************************************************************
-#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
- // Select
-#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
- // Select
-#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
- // Select
-#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
- // Select
-#define ADC_SSDC1_S2DCSEL_S 8
-#define ADC_SSDC1_S1DCSEL_S 4
-#define ADC_SSDC1_S0DCSEL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
-//
-//*****************************************************************************
-#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select
-#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select
-#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select
-#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select
-#define ADC_SSMUX2_MUX3_S 12
-#define ADC_SSMUX2_MUX2_S 8
-#define ADC_SSMUX2_MUX1_S 4
-#define ADC_SSMUX2_MUX0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
-//
-//*****************************************************************************
-#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select
-#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable
-#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence
-#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select
-#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select
-#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable
-#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence
-#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select
-#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select
-#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable
-#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence
-#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select
-#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select
-#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable
-#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence
-#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
-//
-//*****************************************************************************
-#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data
-#define ADC_SSFIFO2_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
-//
-//*****************************************************************************
-#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full
-#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty
-#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer
-#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer
-#define ADC_SSFSTAT2_HPTR_S 4
-#define ADC_SSFSTAT2_TPTR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSOP2 register.
-//
-//*****************************************************************************
-#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator
- // Operation
-#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator
- // Operation
-#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator
- // Operation
-#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator
- // Operation
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSDC2 register.
-//
-//*****************************************************************************
-#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
- // Select
-#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
- // Select
-#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
- // Select
-#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
- // Select
-#define ADC_SSDC2_S2DCSEL_S 8
-#define ADC_SSDC2_S1DCSEL_S 4
-#define ADC_SSDC2_S0DCSEL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
-//
-//*****************************************************************************
-#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select
-#define ADC_SSMUX3_MUX0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
-//
-//*****************************************************************************
-#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select
-#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable
-#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence
-#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
-//
-//*****************************************************************************
-#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data
-#define ADC_SSFIFO3_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
-//
-//*****************************************************************************
-#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full
-#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty
-#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer
-#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer
-#define ADC_SSFSTAT3_HPTR_S 4
-#define ADC_SSFSTAT3_TPTR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSOP3 register.
-//
-//*****************************************************************************
-#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator
- // Operation
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_SSDC3 register.
-//
-//*****************************************************************************
-#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
- // Select
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCRIC register.
-//
-//*****************************************************************************
-#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7
-#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6
-#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5
-#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4
-#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3
-#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2
-#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1
-#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0
-#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7
-#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6
-#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5
-#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4
-#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3
-#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2
-#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1
-#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
-//
-//*****************************************************************************
-#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable
-#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition
-#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band
-#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band
-#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band
-#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode
-#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always
-#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once
-#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always
-#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
-//
-//*****************************************************************************
-#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable
-#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition
-#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band
-#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band
-#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band
-#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode
-#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always
-#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once
-#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always
-#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
-//
-//*****************************************************************************
-#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable
-#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition
-#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band
-#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band
-#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band
-#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode
-#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always
-#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once
-#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always
-#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
-//
-//*****************************************************************************
-#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable
-#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition
-#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band
-#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band
-#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band
-#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode
-#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always
-#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once
-#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always
-#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
-//
-//*****************************************************************************
-#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable
-#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition
-#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band
-#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band
-#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band
-#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode
-#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always
-#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once
-#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always
-#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
-//
-//*****************************************************************************
-#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable
-#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition
-#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band
-#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band
-#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band
-#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode
-#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always
-#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once
-#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always
-#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
-//
-//*****************************************************************************
-#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable
-#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition
-#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band
-#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band
-#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band
-#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode
-#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always
-#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once
-#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always
-#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
-//
-//*****************************************************************************
-#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable
-#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition
-#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band
-#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band
-#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band
-#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode
-#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always
-#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once
-#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always
-#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
-//
-//*****************************************************************************
-#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1
-#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0
-#define ADC_DCCMP0_COMP1_S 16
-#define ADC_DCCMP0_COMP0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
-//
-//*****************************************************************************
-#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1
-#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0
-#define ADC_DCCMP1_COMP1_S 16
-#define ADC_DCCMP1_COMP0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
-//
-//*****************************************************************************
-#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1
-#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0
-#define ADC_DCCMP2_COMP1_S 16
-#define ADC_DCCMP2_COMP0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
-//
-//*****************************************************************************
-#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1
-#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0
-#define ADC_DCCMP3_COMP1_S 16
-#define ADC_DCCMP3_COMP0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
-//
-//*****************************************************************************
-#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1
-#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0
-#define ADC_DCCMP4_COMP1_S 16
-#define ADC_DCCMP4_COMP0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
-//
-//*****************************************************************************
-#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1
-#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0
-#define ADC_DCCMP5_COMP1_S 16
-#define ADC_DCCMP5_COMP0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
-//
-//*****************************************************************************
-#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1
-#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0
-#define ADC_DCCMP6_COMP1_S 16
-#define ADC_DCCMP6_COMP0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
-//
-//*****************************************************************************
-#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1
-#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0
-#define ADC_DCCMP7_COMP1_S 16
-#define ADC_DCCMP7_COMP0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_PP register.
-//
-//*****************************************************************************
-#define ADC_PP_TS 0x00800000 // Temperature Sensor
-#define ADC_PP_RSL_M 0x007C0000 // Resolution
-#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture
-#define ADC_PP_TYPE_SAR 0x00000000 // SAR
-#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count
-#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count
-#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate
-#define ADC_PP_MSR_125K 0x00000001 // 125 ksps
-#define ADC_PP_MSR_250K 0x00000003 // 250 ksps
-#define ADC_PP_MSR_500K 0x00000005 // 500 ksps
-#define ADC_PP_MSR_1M 0x00000007 // 1 Msps
-#define ADC_PP_RSL_S 18
-#define ADC_PP_DC_S 10
-#define ADC_PP_CH_S 4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_PC register.
-//
-//*****************************************************************************
-#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate
-#define ADC_PC_SR_125K 0x00000001 // 125 ksps
-#define ADC_PC_SR_250K 0x00000003 // 250 ksps
-#define ADC_PC_SR_500K 0x00000005 // 500 ksps
-#define ADC_PC_SR_1M 0x00000007 // 1 Msps
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the ADC_O_CC register.
-//
-//*****************************************************************************
-#define ADC_CC_CS_M 0x0000000F // ADC Clock Source
-#define ADC_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
- // PLL bypass is in effect) or the
- // 16 MHz clock derived from PLL /
- // 25 (default)
-#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMP_O_ACMIS register.
-//
-//*****************************************************************************
-#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
- // Status
-#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
- // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMP_O_ACRIS register.
-//
-//*****************************************************************************
-#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
-#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMP_O_ACINTEN register.
-//
-//*****************************************************************************
-#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
-#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMP_O_ACREFCTL
-// register.
-//
-//*****************************************************************************
-#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
-#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
-#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
-#define COMP_ACREFCTL_VREF_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
-//
-//*****************************************************************************
-#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
-//
-//*****************************************************************************
-#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
-#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
-#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
-#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
-#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
-#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
-#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
-#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
-#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
-#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
-#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
-#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
-#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
-#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
-#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
-#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
-#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
-#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
-//
-//*****************************************************************************
-#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
-//
-//*****************************************************************************
-#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
-#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
-#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
-#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
-#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
- // (VIREF)
-#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
-#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
-#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
-#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
-#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
-#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
-#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
-#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
-#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
-#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
-#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
-#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
-#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the COMP_O_PP register.
-//
-//*****************************************************************************
-#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present
-#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present
-#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present
-#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present
-#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present
-#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_CTL register.
-//
-//*****************************************************************************
-#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
-#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
-#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
-#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
-#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
-#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable
-#define CAN_CTL_INIT 0x00000001 // Initialization
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_STS register.
-//
-//*****************************************************************************
-#define CAN_STS_BOFF 0x00000080 // Bus-Off Status
-#define CAN_STS_EWARN 0x00000040 // Warning Status
-#define CAN_STS_EPASS 0x00000020 // Error Passive
-#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully
-#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
- // Successfully
-#define CAN_STS_LEC_M 0x00000007 // Last Error Code
-#define CAN_STS_LEC_NONE 0x00000000 // No Error
-#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
-#define CAN_STS_LEC_FORM 0x00000002 // Format Error
-#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
-#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
-#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
-#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
-#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_ERR register.
-//
-//*****************************************************************************
-#define CAN_ERR_RP 0x00008000 // Received Error Passive
-#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter
-#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter
-#define CAN_ERR_REC_S 8
-#define CAN_ERR_TEC_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_BIT register.
-//
-//*****************************************************************************
-#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point
-#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point
-#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width
-#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler
-#define CAN_BIT_TSEG2_S 12
-#define CAN_BIT_TSEG1_S 8
-#define CAN_BIT_SJW_S 6
-#define CAN_BIT_BRP_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_INT register.
-//
-//*****************************************************************************
-#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier
-#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
-#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_TST register.
-//
-//*****************************************************************************
-#define CAN_TST_RX 0x00000080 // Receive Observation
-#define CAN_TST_TX_M 0x00000060 // Transmit Control
-#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control
-#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point
-#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low
-#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High
-#define CAN_TST_LBACK 0x00000010 // Loopback Mode
-#define CAN_TST_SILENT 0x00000008 // Silent Mode
-#define CAN_TST_BASIC 0x00000004 // Basic Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_BRPE register.
-//
-//*****************************************************************************
-#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension
-#define CAN_BRPE_BRPE_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
-//
-//*****************************************************************************
-#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag
-#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number
-#define CAN_IF1CRQ_MNUM_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
-//
-//*****************************************************************************
-#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read
-#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits
-#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits
-#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits
-#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
-#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data
-#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request
-#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
-#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
-//
-//*****************************************************************************
-#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
-#define CAN_IF1MSK1_IDMSK_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
-//
-//*****************************************************************************
-#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier
-#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction
-#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask
-#define CAN_IF1MSK2_IDMSK_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
-//
-//*****************************************************************************
-#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier
-#define CAN_IF1ARB1_ID_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
-//
-//*****************************************************************************
-#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid
-#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier
-#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction
-#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier
-#define CAN_IF1ARB2_ID_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
-//
-//*****************************************************************************
-#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data
-#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost
-#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending
-#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask
-#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
-#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable
-#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable
-#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request
-#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer
-#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code
-#define CAN_IF1MCTL_DLC_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
-//
-//*****************************************************************************
-#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data
-#define CAN_IF1DA1_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
-//
-//*****************************************************************************
-#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data
-#define CAN_IF1DA2_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
-//
-//*****************************************************************************
-#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data
-#define CAN_IF1DB1_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
-//
-//*****************************************************************************
-#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data
-#define CAN_IF1DB2_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
-//
-//*****************************************************************************
-#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag
-#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number
-#define CAN_IF2CRQ_MNUM_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
-//
-//*****************************************************************************
-#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read
-#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits
-#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits
-#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits
-#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
-#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data
-#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request
-#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
-#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
-//
-//*****************************************************************************
-#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
-#define CAN_IF2MSK1_IDMSK_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
-//
-//*****************************************************************************
-#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier
-#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction
-#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask
-#define CAN_IF2MSK2_IDMSK_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
-//
-//*****************************************************************************
-#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier
-#define CAN_IF2ARB1_ID_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
-//
-//*****************************************************************************
-#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid
-#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier
-#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction
-#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier
-#define CAN_IF2ARB2_ID_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
-//
-//*****************************************************************************
-#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data
-#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost
-#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending
-#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask
-#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
-#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable
-#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable
-#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request
-#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer
-#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code
-#define CAN_IF2MCTL_DLC_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
-//
-//*****************************************************************************
-#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data
-#define CAN_IF2DA1_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
-//
-//*****************************************************************************
-#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data
-#define CAN_IF2DA2_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
-//
-//*****************************************************************************
-#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data
-#define CAN_IF2DB1_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
-//
-//*****************************************************************************
-#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data
-#define CAN_IF2DB2_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
-//
-//*****************************************************************************
-#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits
-#define CAN_TXRQ1_TXRQST_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
-//
-//*****************************************************************************
-#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits
-#define CAN_TXRQ2_TXRQST_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_NWDA1 register.
-//
-//*****************************************************************************
-#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits
-#define CAN_NWDA1_NEWDAT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_NWDA2 register.
-//
-//*****************************************************************************
-#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits
-#define CAN_NWDA2_NEWDAT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_MSG1INT register.
-//
-//*****************************************************************************
-#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
-#define CAN_MSG1INT_INTPND_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_MSG2INT register.
-//
-//*****************************************************************************
-#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
-#define CAN_MSG2INT_INTPND_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
-//
-//*****************************************************************************
-#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
-#define CAN_MSG1VAL_MSGVAL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
-//
-//*****************************************************************************
-#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
-#define CAN_MSG2VAL_MSGVAL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FADDR register.
-//
-//*****************************************************************************
-#define USB_FADDR_M 0x0000007F // Function Address
-#define USB_FADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_POWER register.
-//
-//*****************************************************************************
-#define USB_POWER_ISOUP 0x00000080 // Isochronous Update
-#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect
-#define USB_POWER_RESET 0x00000008 // RESET Signaling
-#define USB_POWER_RESUME 0x00000004 // RESUME Signaling
-#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode
-#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXIS register.
-//
-//*****************************************************************************
-#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt
-#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt
-#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt
-#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt
-#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt
-#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt
-#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt
-#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXIS register.
-//
-//*****************************************************************************
-#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt
-#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt
-#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt
-#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt
-#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt
-#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt
-#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXIE register.
-//
-//*****************************************************************************
-#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable
-#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable
-#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable
-#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable
-#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable
-#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable
-#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable
-#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
- // Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXIE register.
-//
-//*****************************************************************************
-#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable
-#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable
-#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable
-#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable
-#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable
-#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable
-#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IS register.
-//
-//*****************************************************************************
-#define USB_IS_DISCON 0x00000020 // Session Disconnect
-#define USB_IS_SOF 0x00000008 // Start of Frame
-#define USB_IS_RESET 0x00000004 // RESET Signaling Detected
-#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected
-#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_IE register.
-//
-//*****************************************************************************
-#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt
-#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt
-#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt
-#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt
-#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FRAME register.
-//
-//*****************************************************************************
-#define USB_FRAME_M 0x000007FF // Frame Number
-#define USB_FRAME_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_EPIDX register.
-//
-//*****************************************************************************
-#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index
-#define USB_EPIDX_EPIDX_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TEST register.
-//
-//*****************************************************************************
-#define USB_TEST_FIFOACC 0x00000040 // FIFO Access
-#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO0 register.
-//
-//*****************************************************************************
-#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO0_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO1 register.
-//
-//*****************************************************************************
-#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO1_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO2 register.
-//
-//*****************************************************************************
-#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO2_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO3 register.
-//
-//*****************************************************************************
-#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO3_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO4 register.
-//
-//*****************************************************************************
-#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO4_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO5 register.
-//
-//*****************************************************************************
-#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO5_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO6 register.
-//
-//*****************************************************************************
-#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO6_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FIFO7 register.
-//
-//*****************************************************************************
-#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data
-#define USB_FIFO7_EPDATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
-//
-//*****************************************************************************
-#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
-#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
-#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
-#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
-#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
-#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
-#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
-#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
-#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
-#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
-#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
-//
-//*****************************************************************************
-#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
-#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
-#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
-#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
-#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
-#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
-#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
-#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
-#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
-#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
-#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXFIFOADD
-// register.
-//
-//*****************************************************************************
-#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
-#define USB_TXFIFOADD_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXFIFOADD
-// register.
-//
-//*****************************************************************************
-#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
-#define USB_RXFIFOADD_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CONTIM register.
-//
-//*****************************************************************************
-#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait
-#define USB_CONTIM_WTID_M 0x0000000F // Wait ID
-#define USB_CONTIM_WTCON_S 4
-#define USB_CONTIM_WTID_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_FSEOF register.
-//
-//*****************************************************************************
-#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap
-#define USB_FSEOF_FSEOFG_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_LSEOF register.
-//
-//*****************************************************************************
-#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap
-#define USB_LSEOF_LSEOFG_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CSRL0 register.
-//
-//*****************************************************************************
-#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear
-#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear
-#define USB_CSRL0_STALL 0x00000020 // Send Stall
-#define USB_CSRL0_SETEND 0x00000010 // Setup End
-#define USB_CSRL0_DATAEND 0x00000008 // Data End
-#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled
-#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready
-#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_CSRH0 register.
-//
-//*****************************************************************************
-#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_COUNT0 register.
-//
-//*****************************************************************************
-#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count
-#define USB_COUNT0_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP1_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL1_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH1_MODE 0x00000020 // Mode
-#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP1_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL1_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL1_OVER 0x00000004 // Overrun
-#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT1_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP2_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL2_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH2_MODE 0x00000020 // Mode
-#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP2_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL2_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL2_OVER 0x00000004 // Overrun
-#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT2_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP3_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL3_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH3_MODE 0x00000020 // Mode
-#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP3_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL3_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL3_OVER 0x00000004 // Overrun
-#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT3_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP4_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL4_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH4_MODE 0x00000020 // Mode
-#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP4_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL4_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL4_OVER 0x00000004 // Overrun
-#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT4_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP5_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL5_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH5_MODE 0x00000020 // Mode
-#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP5_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL5_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL5_OVER 0x00000004 // Overrun
-#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT5_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP6_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL6_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH6_MODE 0x00000020 // Mode
-#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP6_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL6_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL6_OVER 0x00000004 // Overrun
-#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT6_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
-//
-//*****************************************************************************
-#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_TXMAXP7_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
-//
-//*****************************************************************************
-#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle
-#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled
-#define USB_TXCSRL7_STALL 0x00000010 // Send STALL
-#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO
-#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun
-#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty
-#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
-//
-//*****************************************************************************
-#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set
-#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers
-#define USB_TXCSRH7_MODE 0x00000020 // Mode
-#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable
-#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle
-#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
-//
-//*****************************************************************************
-#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
-#define USB_RXMAXP7_MAXLOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
-//
-//*****************************************************************************
-#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle
-#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled
-#define USB_RXCSRL7_STALL 0x00000020 // Send STALL
-#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO
-#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error
-#define USB_RXCSRL7_OVER 0x00000004 // Overrun
-#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full
-#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
-//
-//*****************************************************************************
-#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear
-#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers
-#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable
-#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error
-#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET
-#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
-//
-//*****************************************************************************
-#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count
-#define USB_RXCOUNT7_COUNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
-// register.
-//
-//*****************************************************************************
-#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer
- // Disable
-#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer
- // Disable
-#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer
- // Disable
-#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer
- // Disable
-#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
- // Disable
-#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
- // Disable
-#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
- // Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
-// register.
-//
-//*****************************************************************************
-#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer
- // Disable
-#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer
- // Disable
-#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer
- // Disable
-#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer
- // Disable
-#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
- // Disable
-#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
- // Disable
-#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
- // Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRRIS register.
-//
-//*****************************************************************************
-#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRIM register.
-//
-//*****************************************************************************
-#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DRISC register.
-//
-//*****************************************************************************
-#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and
- // Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_DMASEL register.
-//
-//*****************************************************************************
-#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select
-#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select
-#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select
-#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select
-#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select
-#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select
-#define USB_DMASEL_DMACTX_S 20
-#define USB_DMASEL_DMACRX_S 16
-#define USB_DMASEL_DMABTX_S 12
-#define USB_DMASEL_DMABRX_S 8
-#define USB_DMASEL_DMAATX_S 4
-#define USB_DMASEL_DMAARX_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the USB_O_PP register.
-//
-//*****************************************************************************
-#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count
-#define USB_PP_USB_M 0x000000C0 // USB Capability
-#define USB_PP_USB_DEVICE 0x00000040 // DEVICE
-#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST
-#define USB_PP_USB_OTG 0x000000C0 // OTG
-#define USB_PP_PHY 0x00000010 // PHY Present
-#define USB_PP_TYPE_M 0x0000000F // Controller Type
-#define USB_PP_TYPE_0 0x00000000 // The first-generation USB
- // controller
-#define USB_PP_ECNT_S 8
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EESIZE register.
-//
-//*****************************************************************************
-#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks
-#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words
-#define EEPROM_EESIZE_BLKCNT_S 16
-#define EEPROM_EESIZE_WORDCNT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
-//
-//*****************************************************************************
-#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block
-#define EEPROM_EEBLOCK_BLOCK_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EEOFFSET
-// register.
-//
-//*****************************************************************************
-#define EEPROM_EEOFFSET_OFFSET_M \
- 0x0000000F // Current Address Offset
-#define EEPROM_EEOFFSET_OFFSET_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EERDWR register.
-//
-//*****************************************************************************
-#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data
-#define EEPROM_EERDWR_VALUE_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EERDWRINC
-// register.
-//
-//*****************************************************************************
-#define EEPROM_EERDWRINC_VALUE_M \
- 0xFFFFFFFF // EEPROM Read or Write Data with
- // Increment
-#define EEPROM_EERDWRINC_VALUE_S \
- 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EEDONE register.
-//
-//*****************************************************************************
-#define EEPROM_EEDONE_INVPL 0x00000100 // Invalid Program Voltage Level
-#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy
-#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission
-#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy
-#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase
-#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EESUPP register.
-//
-//*****************************************************************************
-#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried
-#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried
-#define EEPROM_EESUPP_EREQ 0x00000002 // Erase Required
-#define EEPROM_EESUPP_START 0x00000001 // Start Erase
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EEUNLOCK
-// register.
-//
-//*****************************************************************************
-#define EEPROM_EEUNLOCK_UNLOCK_M \
- 0xFFFFFFFF // EEPROM Unlock
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EEPROT register.
-//
-//*****************************************************************************
-#define EEPROM_EEPROT_ACC 0x00000008 // Access Control
-#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control
-#define EEPROM_EEPROT_PROT_RWNPW \
- 0x00000000 // This setting is the default. If
- // there is no password, the block
- // is not protected and is readable
- // and writable
-#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the
- // block is readable or writable
- // only when unlocked
-#define EEPROM_EEPROT_PROT_RONPW \
- 0x00000002 // If there is no password, the
- // block is readable, not writable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
-//
-//*****************************************************************************
-#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password
-#define EEPROM_EEPASS0_PASS_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
-//
-//*****************************************************************************
-#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password
-#define EEPROM_EEPASS1_PASS_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
-//
-//*****************************************************************************
-#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password
-#define EEPROM_EEPASS2_PASS_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EEINT register.
-//
-//*****************************************************************************
-#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EEHIDE register.
-//
-//*****************************************************************************
-#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_EEDBGME register.
-//
-//*****************************************************************************
-#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key
-#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase
-#define EEPROM_EEDBGME_KEY_S 16
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the EEPROM_PP register.
-//
-//*****************************************************************************
-#define EEPROM_PP_SIZE_M 0x0000001F // EEPROM Size
-#define EEPROM_PP_SIZE_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSEXC_RIS register.
-//
-//*****************************************************************************
-#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception
- // Raw Interrupt Status
-#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow
- // Exception Raw Interrupt Status
-#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow
- // Exception Raw Interrupt Status
-#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation
- // Raw Interrupt Status
-#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0
- // Exception Raw Interrupt Status
-#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal
- // Exception Raw Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSEXC_IM register.
-//
-//*****************************************************************************
-#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception
- // Interrupt Mask
-#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow
- // Exception Interrupt Mask
-#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow
- // Exception Interrupt Mask
-#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation
- // Interrupt Mask
-#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0
- // Exception Interrupt Mask
-#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal
- // Exception Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSEXC_MIS register.
-//
-//*****************************************************************************
-#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception
- // Masked Interrupt Status
-#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow
- // Exception Masked Interrupt
- // Status
-#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow
- // Exception Masked Interrupt
- // Status
-#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation
- // Masked Interrupt Status
-#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0
- // Exception Masked Interrupt
- // Status
-#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal
- // Exception Masked Interrupt
- // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSEXC_IC register.
-//
-//*****************************************************************************
-#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception
- // Interrupt Clear
-#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow
- // Exception Interrupt Clear
-#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow
- // Exception Interrupt Clear
-#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation
- // Interrupt Clear
-#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0
- // Exception Interrupt Clear
-#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal
- // Exception Interrupt Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HIB_RTCC register.
-//
-//*****************************************************************************
-#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
-#define HIB_RTCC_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HIB_RTCM0 register.
-//
-//*****************************************************************************
-#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
-#define HIB_RTCM0_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HIB_RTCLD register.
-//
-//*****************************************************************************
-#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
-#define HIB_RTCLD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HIB_CTL register.
-//
-//*****************************************************************************
-#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
-#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
-#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
-#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
- // Comparator
-#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
-#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
-#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
-#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
-#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
-#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
-#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
-#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
-#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
-#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable
-#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
-#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
-#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
-#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HIB_IM register.
-//
-//*****************************************************************************
-#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
- // Interrupt Mask
-#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
-#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
- // Mask
-#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HIB_RIS register.
-//
-//*****************************************************************************
-#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
- // Interrupt Status
-#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
- // Status
-#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
- // Interrupt Status
-#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HIB_MIS register.
-//
-//*****************************************************************************
-#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
- // Interrupt Status
-#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
- // Interrupt Status
-#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
- // Interrupt Status
-#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
- // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HIB_IC register.
-//
-//*****************************************************************************
-#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
- // Interrupt Clear
-#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
- // Interrupt Clear
-#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
- // Interrupt Clear
-#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
- // Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HIB_RTCT register.
-//
-//*****************************************************************************
-#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
-#define HIB_RTCT_TRIM_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HIB_RTCSS register.
-//
-//*****************************************************************************
-#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
-#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
-#define HIB_RTCSS_RTCSSM_S 16
-#define HIB_RTCSS_RTCSSC_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the HIB_DATA register.
-//
-//*****************************************************************************
-#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
-#define HIB_DATA_RTD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FMA register.
-//
-//*****************************************************************************
-#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset
-#define FLASH_FMA_OFFSET_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FMD register.
-//
-//*****************************************************************************
-#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
-#define FLASH_FMD_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FMC register.
-//
-//*****************************************************************************
-#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
-#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
-#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
-#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
-#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FCRIS register.
-//
-//*****************************************************************************
-#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status
-#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status
-#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
- // Status
-#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status
-#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
-#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
-#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FCIM register.
-//
-//*****************************************************************************
-#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
-#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
-#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
-#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
-#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
-#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
-#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FCMISC register.
-//
-//*****************************************************************************
-#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
- // and Clear
-#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
- // and Clear
-#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
- // Status and Clear
-#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
- // Clear
-#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
- // and Clear
-#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
- // Status and Clear
-#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
- // and Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FMC2 register.
-//
-//*****************************************************************************
-#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
-#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FWBVAL register.
-//
-//*****************************************************************************
-#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FWBN register.
-//
-//*****************************************************************************
-#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_FSIZE register.
-//
-//*****************************************************************************
-#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
-#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash
-#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash
-#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
-#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
-#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash
-#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
-#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash
-#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_SSIZE register.
-//
-//*****************************************************************************
-#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
-#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM
-#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM
-#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM
-#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM
-#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
-#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM
-#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM
-#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
-#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
-//
-//*****************************************************************************
-#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_RMCTL register.
-//
-//*****************************************************************************
-#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_BOOTCFG register.
-//
-//*****************************************************************************
-#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
-#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
-#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
-#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
-#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
-#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
-#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
-#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
-#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
-#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
-#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
-#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
-#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1
-#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2
-#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
-#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4
-#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5
-#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6
-#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
-#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
-#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
-#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
-#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERREG0 register.
-//
-//*****************************************************************************
-#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data
-#define FLASH_USERREG0_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERREG1 register.
-//
-//*****************************************************************************
-#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data
-#define FLASH_USERREG1_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERREG2 register.
-//
-//*****************************************************************************
-#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data
-#define FLASH_USERREG2_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the FLASH_USERREG3 register.
-//
-//*****************************************************************************
-#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data
-#define FLASH_USERREG3_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DID0 register.
-//
-//*****************************************************************************
-#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version
-#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
- // register format
-#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
-#define SYSCTL_DID0_CLASS_BLIZZARD \
- 0x00050000 // Stellaris(R) Blizzard-class
- // microcontrollers
-#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision
-#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
-#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
- // revision)
-#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
- // revision)
-#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision
-#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
- // revision update
-#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change
-#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DID1 register.
-//
-//*****************************************************************************
-#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version
-#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format
- // definition, indicating a
- // Stellaris LM3Snnn device
-#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1
- // register format
-#define SYSCTL_DID1_FAM_M 0x0F000000 // Family
-#define SYSCTL_DID1_FAM_STELLARIS \
- 0x00000000 // Stellaris family of
- // microcontollers, that is, all
- // devices with external part
- // numbers starting with LM3S
-#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number
-#define SYSCTL_DID1_PRTNO_LM4F120H5QR \
- 0x00040000 // LM4F120H5QR
-#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count
-#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28-pin package
-#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package
-#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package
-#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package
-#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin package
-#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin package
-#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range
-#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C
- // to 70C)
-#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
- // (-40C to 85C)
-#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
- // to 105C)
-#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type
-#define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package
-#define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package
-#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
-#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance
-#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status
-#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
-#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
-#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC0 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size
-#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM
-#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
-#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size
-#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash
-#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash
-#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash
-#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash
-#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash
-#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash
-#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash
-#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
-#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
-#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC1 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present
-#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present
-#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present
-#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present
-#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present
-#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present
-#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present
-#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider
-#define SYSCTL_DC1_MINSYSDIV_100 \
- 0x00001000 // Divide VCO (400MHZ) by 5 minimum
-#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Divide VCO (400MHZ) by 2*2 + 2 =
- // 6 minimum
-#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
- // with a PLL divider of 4
-#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock
- // with a PLL divider of 5
-#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
- // PLL divider of 8
-#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
- // PLL divider of 10
-#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed
-#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second
-#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second
-#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second
-#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
-#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed
-#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second
-#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second
-#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second
-#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
-#define SYSCTL_DC1_MPU 0x00000080 // MPU Present
-#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present
-#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present
-#define SYSCTL_DC1_PLL 0x00000010 // PLL Present
-#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present
-#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present
-#define SYSCTL_DC1_SWD 0x00000002 // SWD Present
-#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present
-#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present
-#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present
-#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present
-#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present
-#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present
-#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present
-#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present
-#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present
-#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed
-#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present
-#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed
-#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present
-#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present
-#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present
-#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present
-#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present
-#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present
-#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present
-#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC3 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available
-#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 Pin Present
-#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 Pin Present
-#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present
-#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present
-#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present
-#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present
-#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present
-#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present
-#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present
-#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present
-#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present
-#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present
-#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present
-#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present
-#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present
-#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present
-#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present
-#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present
-#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present
-#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present
-#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present
-#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present
-#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present
-#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present
-#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present
-#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present
-#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present
-#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present
-#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present
-#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC4 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present
-#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present
-#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable
-#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate
-#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present
-#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present
-#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present
-#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present
-#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present
-#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present
-#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present
-#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present
-#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present
-#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present
-#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present
-#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present
-#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC5 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present
-#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present
-#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present
-#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present
-#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active
-#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active
-#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present
-#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present
-#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present
-#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present
-#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present
-#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present
-#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present
-#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC6 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present
-#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present
-#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only
-#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host
-#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC7 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC7_DMACH30 0x40000000 // SW
-#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX / CAN1_TX
-#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX / CAN1_RX
-#define SYSCTL_DC7_DMACH27 0x08000000 // CAN1_TX / ADC1_SS3
-#define SYSCTL_DC7_DMACH26 0x04000000 // CAN1_RX / ADC1_SS2
-#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1
-#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0
-#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX / CAN2_TX
-#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX / CAN2_RX
-#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_WFIFO
-#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_NBRFIFO
-#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B
-#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A
-#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3
-#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2
-#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B
-#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A
-#define SYSCTL_DC7_DMACH13 0x00002000 // CAN0_TX / UART2_TX
-#define SYSCTL_DC7_DMACH12 0x00001000 // CAN0_RX / UART2_RX
-#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / SSI1_TX
-#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / SSI1_RX
-#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / UART1_TX
-#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / UART1_RX
-#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B
-#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A
-#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B
-#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A
-#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B
-#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A
-#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX
-#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC8 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present
-#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present
-#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present
-#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present
-#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present
-#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present
-#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present
-#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present
-#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present
-#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present
-#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present
-#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present
-#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present
-#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present
-#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present
-#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present
-#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present
-#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present
-#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present
-#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present
-#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present
-#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present
-#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present
-#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present
-#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present
-#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present
-#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present
-#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present
-#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present
-#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present
-#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present
-#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
-//
-//*****************************************************************************
-#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
-//
-//*****************************************************************************
-#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control
-#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control
-#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control
-#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control
-#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control
-#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control
-#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control
-#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
-//
-//*****************************************************************************
-#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control
-#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control
-#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control
-#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control
-#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control
-#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control
-#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control
-#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control
-#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control
-#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control
-#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control
-#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control
-#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control
-#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control
-#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control
-#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
-//
-//*****************************************************************************
-#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control
-#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control
-#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control
-#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control
-#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control
-#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control
-#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control
-#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control
-#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control
-#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control
-#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RIS register.
-//
-//*****************************************************************************
-#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
- // Status
-#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt
- // Status
-#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status
-#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw
- // Interrupt Status
-#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
- // Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_IMC register.
-//
-//*****************************************************************************
-#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask
-#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask
-#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask
-#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt
- // Mask
-#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_MISC register.
-//
-//*****************************************************************************
-#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
- // Status
-#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt
- // Status
-#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status
-#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked
- // Interrupt Status
-#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RESC register.
-//
-//*****************************************************************************
-#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset
-#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset
-#define SYSCTL_RESC_SW 0x00000010 // Software Reset
-#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset
-#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset
-#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset
-#define SYSCTL_RESC_EXT 0x00000001 // External Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCC register.
-//
-//*****************************************************************************
-#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating
-#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor
-#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider
-#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down
-#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass
-#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value
-#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz
-#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
-#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
-#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz
-#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
-#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz
-#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
-#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
-#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz
-#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
-#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz
-#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz
-#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz
-#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz
-#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
-#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz
-#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
-#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz
-#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz
-#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz
-#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz
-#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source
-#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
-#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC
-#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4
-#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz
-#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable
-#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable
-#define SYSCTL_RCC_SYSDIV_S 23
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance
- // Bus
-#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance
- // Bus
-#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance
- // Bus
-#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance
- // Bus
-#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance
- // Bus
-#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance
- // Bus
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
-#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200
- // MHz
-#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2
-#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
-#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
-#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
-#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
-#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
-#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
-#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
-#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
-#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
-#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
-#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
-#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
-#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
-#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
-#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
-#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
-#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
-#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
-#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
-#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
-#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
-#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
-#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
-#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
-#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
-#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
-#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
-#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
-#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
-#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
-#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
-#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
-#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
-#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
-#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
-#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
-#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
-#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
-#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
-#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
-#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
-#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
-#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
-#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
-#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
-#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
-#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
-#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
-#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
-#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
-#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
-#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
-#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
-#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
-#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
-#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
-#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
-#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
-#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
-#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
-#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
-#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
-#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
-#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2
-#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL
-#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2
-#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2
-#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2
-#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
-#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC
-#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4
-#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz
-#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz
-#define SYSCTL_RCC2_SYSDIV2_S 23
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
-//
-//*****************************************************************************
-#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected
-#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action
-#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
-#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
-#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
-#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control
-#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
-#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
-#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed
-#define SYSCTL_RCGC0_ADC1SPD_125K \
- 0x00000000 // 125K samples/second
-#define SYSCTL_RCGC0_ADC1SPD_250K \
- 0x00000400 // 250K samples/second
-#define SYSCTL_RCGC0_ADC1SPD_500K \
- 0x00000800 // 500K samples/second
-#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
-#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed
-#define SYSCTL_RCGC0_ADC0SPD_125K \
- 0x00000000 // 125K samples/second
-#define SYSCTL_RCGC0_ADC0SPD_250K \
- 0x00000100 // 250K samples/second
-#define SYSCTL_RCGC0_ADC0SPD_500K \
- 0x00000200 // 500K samples/second
-#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
-#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control
-#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
-#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
-#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
-#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
-#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
-#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
-#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
-#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
-#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
-#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
-#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
-#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
-#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
-#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control
-#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control
-#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control
-#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
-#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
-#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
-#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
-#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
-#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
-#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
-#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
-#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
-#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
-#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
-#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
-#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control
-#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
-#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
-#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control
-#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
-#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
-#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
-#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
-#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
-#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
-#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
-#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
-#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
-#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
-#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
-#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
-#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
-#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control
-#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control
-#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control
-#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
-#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
-#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
-#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
-#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
-#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
-#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
-#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
-#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
-#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
-#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
-#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
-#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control
-#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
-#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
-#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control
-#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
-#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
-#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
-#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
-#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
-#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
-#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
-#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
-#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
-#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
-#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
-#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
-#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
-#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control
-#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control
-#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control
-#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
-#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
-#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
-#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
-#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
-#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
-#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
-#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
-#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
-#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override
-#define SYSCTL_DSLPCLKCFG_D_1 0x00000000 // System clock /1
-#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2
-#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3
-#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4
-#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64
-#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source
-#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
-#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC
-#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz
-#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
-//
-//*****************************************************************************
-#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value
-#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration
-#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim
-#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value
-#define SYSCTL_PIOSCCAL_UT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value
-#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result
-#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been
- // attempted
-#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation
- // completed to meet 1% accuracy
-#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation
- // failed to meet 1% accuracy
-#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value
-#define SYSCTL_PIOSCSTAT_DT_S 16
-#define SYSCTL_PIOSCSTAT_CT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value
-#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value
-#define SYSCTL_PLLFREQ0_MFRAC_S 10
-#define SYSCTL_PLLFREQ0_MINT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value
-#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value
-#define SYSCTL_PLLFREQ1_Q_S 8
-#define SYSCTL_PLLFREQ1_N_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
-//
-//*****************************************************************************
-#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DC9 register.
-//
-//*****************************************************************************
-#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present
-#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present
-#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present
-#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present
-#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present
-#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present
-#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present
-#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present
-#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present
-#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present
-#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present
-#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present
-#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present
-#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present
-#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present
-#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
-//
-//*****************************************************************************
-#define SYSCTL_NVMSTAT_TPSW 0x00000010 // Third Party Software Present
-#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer
- // Active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPWD register.
-//
-//*****************************************************************************
-#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present
-#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPTIMER register.
-//
-//*****************************************************************************
-#define SYSCTL_PPTIMER_P5 0x00000020 // Timer 5 Present
-#define SYSCTL_PPTIMER_P4 0x00000010 // Timer 4 Present
-#define SYSCTL_PPTIMER_P3 0x00000008 // Timer 3 Present
-#define SYSCTL_PPTIMER_P2 0x00000004 // Timer 2 Present
-#define SYSCTL_PPTIMER_P1 0x00000002 // Timer 1 Present
-#define SYSCTL_PPTIMER_P0 0x00000001 // Timer 0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPGPIO register.
-//
-//*****************************************************************************
-#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present
-#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present
-#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present
-#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present
-#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present
-#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present
-#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present
-#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present
-#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present
-#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present
-#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present
-#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present
-#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present
-#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present
-#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPDMA register.
-//
-//*****************************************************************************
-#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPHIB register.
-//
-//*****************************************************************************
-#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPUART register.
-//
-//*****************************************************************************
-#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present
-#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present
-#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present
-#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present
-#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present
-#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present
-#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present
-#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPSSI register.
-//
-//*****************************************************************************
-#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present
-#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present
-#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present
-#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPI2C register.
-//
-//*****************************************************************************
-#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present
-#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present
-#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present
-#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present
-#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present
-#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPUSB register.
-//
-//*****************************************************************************
-#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPCAN register.
-//
-//*****************************************************************************
-#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present
-#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPADC register.
-//
-//*****************************************************************************
-#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present
-#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPACMP register.
-//
-//*****************************************************************************
-#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPPWM register.
-//
-//*****************************************************************************
-#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present
-#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPQEI register.
-//
-//*****************************************************************************
-#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present
-#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPEEPROM
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PPWTIMER
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_PPWTIMER_P5 0x00000020 // Wide Timer 5 Present
-#define SYSCTL_PPWTIMER_P4 0x00000010 // Wide Timer 4 Present
-#define SYSCTL_PPWTIMER_P3 0x00000008 // Wide Timer 3 Present
-#define SYSCTL_PPWTIMER_P2 0x00000004 // Wide Timer 2 Present
-#define SYSCTL_PPWTIMER_P1 0x00000002 // Wide Timer 1 Present
-#define SYSCTL_PPWTIMER_P0 0x00000001 // Wide Timer 0 Present
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRWD register.
-//
-//*****************************************************************************
-#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset
-#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRTIMER register.
-//
-//*****************************************************************************
-#define SYSCTL_SRTIMER_R5 0x00000020 // Timer 5 Software Reset
-#define SYSCTL_SRTIMER_R4 0x00000010 // Timer 4 Software Reset
-#define SYSCTL_SRTIMER_R3 0x00000008 // Timer 3 Software Reset
-#define SYSCTL_SRTIMER_R2 0x00000004 // Timer 2 Software Reset
-#define SYSCTL_SRTIMER_R1 0x00000002 // Timer 1 Software Reset
-#define SYSCTL_SRTIMER_R0 0x00000001 // Timer 0 Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRGPIO register.
-//
-//*****************************************************************************
-#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset
-#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset
-#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset
-#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset
-#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset
-#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset
-#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset
-#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset
-#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset
-#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset
-#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset
-#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset
-#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset
-#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset
-#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRDMA register.
-//
-//*****************************************************************************
-#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRHIB register.
-//
-//*****************************************************************************
-#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software
- // Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRUART register.
-//
-//*****************************************************************************
-#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset
-#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset
-#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset
-#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset
-#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset
-#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset
-#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset
-#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRSSI register.
-//
-//*****************************************************************************
-#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset
-#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset
-#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset
-#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRI2C register.
-//
-//*****************************************************************************
-#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset
-#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset
-#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset
-#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset
-#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset
-#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRUSB register.
-//
-//*****************************************************************************
-#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRCAN register.
-//
-//*****************************************************************************
-#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset
-#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRADC register.
-//
-//*****************************************************************************
-#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset
-#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRACMP register.
-//
-//*****************************************************************************
-#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0
- // Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SREEPROM
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SRWTIMER
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_SRWTIMER_R5 0x00000020 // Wide Timer 5 Software Reset
-#define SYSCTL_SRWTIMER_R4 0x00000010 // Wide Timer 4 Software Reset
-#define SYSCTL_SRWTIMER_R3 0x00000008 // Wide Timer 3 Software Reset
-#define SYSCTL_SRWTIMER_R2 0x00000004 // Wide Timer 2 Software Reset
-#define SYSCTL_SRWTIMER_R1 0x00000002 // Wide Timer 1 Software Reset
-#define SYSCTL_SRWTIMER_R0 0x00000001 // Wide Timer 0 Software Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCWD register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCTIMER
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCTIMER_R5 0x00000020 // Timer 5 Run Mode Clock Gating
- // Control
-#define SYSCTL_RCGCTIMER_R4 0x00000010 // Timer 4 Run Mode Clock Gating
- // Control
-#define SYSCTL_RCGCTIMER_R3 0x00000008 // Timer 3 Run Mode Clock Gating
- // Control
-#define SYSCTL_RCGCTIMER_R2 0x00000004 // Timer 2 Run Mode Clock Gating
- // Control
-#define SYSCTL_RCGCTIMER_R1 0x00000002 // Timer 1 Run Mode Clock Gating
- // Control
-#define SYSCTL_RCGCTIMER_R0 0x00000001 // Timer 0 Run Mode Clock Gating
- // Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCGPIO
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCUART
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating
- // Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCADC register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCACMP
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run
- // Mode Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_RCGCWTIMER_R5 0x00000020 // Wide Timer 5 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCWTIMER_R4 0x00000010 // Wide Timer 4 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCWTIMER_R3 0x00000008 // Wide Timer 3 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCWTIMER_R2 0x00000004 // Wide Timer 2 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCWTIMER_R1 0x00000002 // Wide Timer 1 Run Mode Clock
- // Gating Control
-#define SYSCTL_RCGCWTIMER_R0 0x00000001 // Wide Timer 0 Run Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCWD register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode
- // Clock Gating Control
-#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCTIMER
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCTIMER_S5 0x00000020 // Timer 5 Sleep Mode Clock Gating
- // Control
-#define SYSCTL_SCGCTIMER_S4 0x00000010 // Timer 4 Sleep Mode Clock Gating
- // Control
-#define SYSCTL_SCGCTIMER_S3 0x00000008 // Timer 3 Sleep Mode Clock Gating
- // Control
-#define SYSCTL_SCGCTIMER_S2 0x00000004 // Timer 2 Sleep Mode Clock Gating
- // Control
-#define SYSCTL_SCGCTIMER_S1 0x00000002 // Timer 1 Sleep Mode Clock Gating
- // Control
-#define SYSCTL_SCGCTIMER_S0 0x00000001 // Timer 0 Sleep Mode Clock Gating
- // Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCGPIO
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCUART
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCADC register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCACMP
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep
- // Mode Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_SCGCWTIMER_S5 0x00000020 // Wide Timer 5 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCWTIMER_S4 0x00000010 // Wide Timer 4 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCWTIMER_S3 0x00000008 // Wide Timer 3 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCWTIMER_S2 0x00000004 // Wide Timer 2 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCWTIMER_S1 0x00000002 // Wide Timer 1 Sleep Mode Clock
- // Gating Control
-#define SYSCTL_SCGCWTIMER_S0 0x00000001 // Wide Timer 0 Sleep Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCWD register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCTIMER
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCTIMER_D5 0x00000020 // Timer 5 Deep-Sleep Mode Clock
- // Gating Control
-#define SYSCTL_DCGCTIMER_D4 0x00000010 // Timer 4 Deep-Sleep Mode Clock
- // Gating Control
-#define SYSCTL_DCGCTIMER_D3 0x00000008 // Timer 3 Deep-Sleep Mode Clock
- // Gating Control
-#define SYSCTL_DCGCTIMER_D2 0x00000004 // Timer 2 Deep-Sleep Mode Clock
- // Gating Control
-#define SYSCTL_DCGCTIMER_D1 0x00000002 // Timer 1 Deep-Sleep Mode Clock
- // Gating Control
-#define SYSCTL_DCGCTIMER_D0 0x00000001 // Timer 0 Deep-Sleep Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCGPIO
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep
- // Mode Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCUART
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock
- // Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCADC register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCACMP
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0
- // Deep-Sleep Mode Clock Gating
- // Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_DCGCWTIMER_D5 0x00000020 // Wide Timer 5 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCWTIMER_D4 0x00000010 // Wide Timer 4 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCWTIMER_D3 0x00000008 // Wide Timer 3 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCWTIMER_D2 0x00000004 // Wide Timer 2 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCWTIMER_D1 0x00000002 // Wide Timer 1 Deep-Sleep Mode
- // Clock Gating Control
-#define SYSCTL_DCGCWTIMER_D0 0x00000001 // Wide Timer 0 Deep-Sleep Mode
- // Clock Gating Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCWD register.
-//
-//*****************************************************************************
-#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control
-#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCTIMER register.
-//
-//*****************************************************************************
-#define SYSCTL_PCTIMER_P5 0x00000020 // Timer 5 Power Control
-#define SYSCTL_PCTIMER_P4 0x00000010 // Timer 4 Power Control
-#define SYSCTL_PCTIMER_P3 0x00000008 // Timer 3 Power Control
-#define SYSCTL_PCTIMER_P2 0x00000004 // Timer 2 Power Control
-#define SYSCTL_PCTIMER_P1 0x00000002 // Timer 1 Power Control
-#define SYSCTL_PCTIMER_P0 0x00000001 // Timer 0 Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCGPIO register.
-//
-//*****************************************************************************
-#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control
-#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control
-#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control
-#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control
-#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control
-#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control
-#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control
-#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control
-#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control
-#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control
-#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control
-#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control
-#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control
-#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control
-#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCDMA register.
-//
-//*****************************************************************************
-#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCHIB register.
-//
-//*****************************************************************************
-#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCUART register.
-//
-//*****************************************************************************
-#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control
-#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control
-#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control
-#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control
-#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control
-#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control
-#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control
-#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCSSI register.
-//
-//*****************************************************************************
-#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control
-#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control
-#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control
-#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCI2C register.
-//
-//*****************************************************************************
-#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control
-#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control
-#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control
-#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control
-#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control
-#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCUSB register.
-//
-//*****************************************************************************
-#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCCAN register.
-//
-//*****************************************************************************
-#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control
-#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCADC register.
-//
-//*****************************************************************************
-#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control
-#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCACMP register.
-//
-//*****************************************************************************
-#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power
- // Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCEEPROM
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PCWTIMER
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_PCWTIMER_P5 0x00000020 // Wide Timer 5 Power Control
-#define SYSCTL_PCWTIMER_P4 0x00000010 // Wide Timer 4 Power Control
-#define SYSCTL_PCWTIMER_P3 0x00000008 // Wide Timer 3 Power Control
-#define SYSCTL_PCWTIMER_P2 0x00000004 // Wide Timer 2 Power Control
-#define SYSCTL_PCWTIMER_P1 0x00000002 // Wide Timer 1 Power Control
-#define SYSCTL_PCWTIMER_P0 0x00000001 // Wide Timer 0 Power Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRWD register.
-//
-//*****************************************************************************
-#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral
- // Ready
-#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral
- // Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRTIMER register.
-//
-//*****************************************************************************
-#define SYSCTL_PRTIMER_R5 0x00000020 // Timer 5 Peripheral Ready
-#define SYSCTL_PRTIMER_R4 0x00000010 // Timer 4 Peripheral Ready
-#define SYSCTL_PRTIMER_R3 0x00000008 // Timer 3 Peripheral Ready
-#define SYSCTL_PRTIMER_R2 0x00000004 // Timer 2 Peripheral Ready
-#define SYSCTL_PRTIMER_R1 0x00000002 // Timer 1 Peripheral Ready
-#define SYSCTL_PRTIMER_R0 0x00000001 // Timer 0 Peripheral Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRGPIO register.
-//
-//*****************************************************************************
-#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready
-#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready
-#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready
-#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready
-#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready
-#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready
-#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready
-#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready
-#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready
-#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready
-#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready
-#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready
-#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready
-#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready
-#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRDMA register.
-//
-//*****************************************************************************
-#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRHIB register.
-//
-//*****************************************************************************
-#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral
- // Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRUART register.
-//
-//*****************************************************************************
-#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready
-#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready
-#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready
-#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready
-#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready
-#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready
-#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready
-#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRSSI register.
-//
-//*****************************************************************************
-#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready
-#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready
-#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready
-#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRI2C register.
-//
-//*****************************************************************************
-#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready
-#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready
-#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready
-#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready
-#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready
-#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRUSB register.
-//
-//*****************************************************************************
-#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRCAN register.
-//
-//*****************************************************************************
-#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready
-#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRADC register.
-//
-//*****************************************************************************
-#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready
-#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRACMP register.
-//
-//*****************************************************************************
-#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0
- // Peripheral Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PREEPROM
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the SYSCTL_PRWTIMER
-// register.
-//
-//*****************************************************************************
-#define SYSCTL_PRWTIMER_R5 0x00000020 // Wide Timer 5 Peripheral Ready
-#define SYSCTL_PRWTIMER_R4 0x00000010 // Wide Timer 4 Peripheral Ready
-#define SYSCTL_PRWTIMER_R3 0x00000008 // Wide Timer 3 Peripheral Ready
-#define SYSCTL_PRWTIMER_R2 0x00000004 // Wide Timer 2 Peripheral Ready
-#define SYSCTL_PRWTIMER_R1 0x00000002 // Wide Timer 1 Peripheral Ready
-#define SYSCTL_PRWTIMER_R0 0x00000001 // Wide Timer 0 Peripheral Ready
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_STAT register.
-//
-//*****************************************************************************
-#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
-#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
-#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
-#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
-#define UDMA_STAT_STATE_RD_SRCENDP \
- 0x00000020 // Reading source end pointer
-#define UDMA_STAT_STATE_RD_DSTENDP \
- 0x00000030 // Reading destination end pointer
-#define UDMA_STAT_STATE_RD_SRCDAT \
- 0x00000040 // Reading source data
-#define UDMA_STAT_STATE_WR_DSTDAT \
- 0x00000050 // Writing destination data
-#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to
- // clear
-#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
-#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
-#define UDMA_STAT_STATE_DONE 0x00000090 // Done
-#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
-#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
-#define UDMA_STAT_DMACHANS_S 16
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CFG register.
-//
-//*****************************************************************************
-#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CTLBASE register.
-//
-//*****************************************************************************
-#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
-#define UDMA_CTLBASE_ADDR_S 10
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ALTBASE register.
-//
-//*****************************************************************************
-#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
- // Pointer
-#define UDMA_ALTBASE_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_WAITSTAT register.
-//
-//*****************************************************************************
-#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_SWREQ register.
-//
-//*****************************************************************************
-#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_USEBURSTSET
-// register.
-//
-//*****************************************************************************
-#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_USEBURSTCLR
-// register.
-//
-//*****************************************************************************
-#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_REQMASKSET
-// register.
-//
-//*****************************************************************************
-#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_REQMASKCLR
-// register.
-//
-//*****************************************************************************
-#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ENASET register.
-//
-//*****************************************************************************
-#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ENACLR register.
-//
-//*****************************************************************************
-#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ALTSET register.
-//
-//*****************************************************************************
-#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ALTCLR register.
-//
-//*****************************************************************************
-#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_PRIOSET register.
-//
-//*****************************************************************************
-#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_PRIOCLR register.
-//
-//*****************************************************************************
-#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_ERRCLR register.
-//
-//*****************************************************************************
-#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CHASGN register.
-//
-//*****************************************************************************
-#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
-#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel
- // assignment
-#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel
- // assignment
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CHIS register.
-//
-//*****************************************************************************
-#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CHMAP0 register.
-//
-//*****************************************************************************
-#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
-#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
-#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
-#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
-#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
-#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
-#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
-#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
-#define UDMA_CHMAP0_CH7SEL_S 28
-#define UDMA_CHMAP0_CH6SEL_S 24
-#define UDMA_CHMAP0_CH5SEL_S 20
-#define UDMA_CHMAP0_CH4SEL_S 16
-#define UDMA_CHMAP0_CH3SEL_S 12
-#define UDMA_CHMAP0_CH2SEL_S 8
-#define UDMA_CHMAP0_CH1SEL_S 4
-#define UDMA_CHMAP0_CH0SEL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CHMAP1 register.
-//
-//*****************************************************************************
-#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
-#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
-#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
-#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
-#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
-#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
-#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
-#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
-#define UDMA_CHMAP1_CH15SEL_S 28
-#define UDMA_CHMAP1_CH14SEL_S 24
-#define UDMA_CHMAP1_CH13SEL_S 20
-#define UDMA_CHMAP1_CH12SEL_S 16
-#define UDMA_CHMAP1_CH11SEL_S 12
-#define UDMA_CHMAP1_CH10SEL_S 8
-#define UDMA_CHMAP1_CH9SEL_S 4
-#define UDMA_CHMAP1_CH8SEL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CHMAP2 register.
-//
-//*****************************************************************************
-#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
-#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
-#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
-#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
-#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
-#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
-#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
-#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
-#define UDMA_CHMAP2_CH23SEL_S 28
-#define UDMA_CHMAP2_CH22SEL_S 24
-#define UDMA_CHMAP2_CH21SEL_S 20
-#define UDMA_CHMAP2_CH20SEL_S 16
-#define UDMA_CHMAP2_CH19SEL_S 12
-#define UDMA_CHMAP2_CH18SEL_S 8
-#define UDMA_CHMAP2_CH17SEL_S 4
-#define UDMA_CHMAP2_CH16SEL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_CHMAP3 register.
-//
-//*****************************************************************************
-#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
-#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
-#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
-#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
-#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
-#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
-#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
-#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
-#define UDMA_CHMAP3_CH31SEL_S 28
-#define UDMA_CHMAP3_CH30SEL_S 24
-#define UDMA_CHMAP3_CH29SEL_S 20
-#define UDMA_CHMAP3_CH28SEL_S 16
-#define UDMA_CHMAP3_CH27SEL_S 12
-#define UDMA_CHMAP3_CH26SEL_S 8
-#define UDMA_CHMAP3_CH25SEL_S 4
-#define UDMA_CHMAP3_CH24SEL_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
-//
-//*****************************************************************************
-#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
-#define UDMA_SRCENDP_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
-//
-//*****************************************************************************
-#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
-#define UDMA_DSTENDP_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the UDMA_O_CHCTL register.
-//
-//*****************************************************************************
-#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
-#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
-#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
-#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
-#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
-#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
-#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
-#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
-#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
-#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
-#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
-#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
-#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
-#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
-#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
-#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
-#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
-#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
-#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
-#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
-#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
-#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
-#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
-#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
-#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
-#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
-#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
-#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
-#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
-#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
-#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
-#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
-#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
-#define UDMA_CHCTL_XFERMODE_STOP \
- 0x00000000 // Stop
-#define UDMA_CHCTL_XFERMODE_BASIC \
- 0x00000001 // Basic
-#define UDMA_CHCTL_XFERMODE_AUTO \
- 0x00000002 // Auto-Request
-#define UDMA_CHCTL_XFERMODE_PINGPONG \
- 0x00000003 // Ping-Pong
-#define UDMA_CHCTL_XFERMODE_MEM_SG \
- 0x00000004 // Memory Scatter-Gather
-#define UDMA_CHCTL_XFERMODE_MEM_SGA \
- 0x00000005 // Alternate Memory Scatter-Gather
-#define UDMA_CHCTL_XFERMODE_PER_SG \
- 0x00000006 // Peripheral Scatter-Gather
-#define UDMA_CHCTL_XFERMODE_PER_SGA \
- 0x00000007 // Alternate Peripheral
- // Scatter-Gather
-#define UDMA_CHCTL_XFERSIZE_S 4
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_INT_TYPE register.
-//
-//*****************************************************************************
-#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
-#define NVIC_INT_TYPE_LINES_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTLR register.
-//
-//*****************************************************************************
-#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating
- // Point
-#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL
-#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding
-#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer
-#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple
- // Cycle Instructions
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ST_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag
-#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
-#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable
-#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
-//
-//*****************************************************************************
-#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value
-#define NVIC_ST_RELOAD_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ST_CURRENT
-// register.
-//
-//*****************************************************************************
-#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value
-#define NVIC_ST_CURRENT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ST_CAL register.
-//
-//*****************************************************************************
-#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
-#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
-#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
-#define NVIC_ST_CAL_ONEMS_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_EN0 register.
-//
-//*****************************************************************************
-#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable
-#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
-#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
-#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
-#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
-#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
-#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
-#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
-#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
-#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
-#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
-#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
-#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
-#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
-#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
-#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
-#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
-#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
-#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
-#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
-#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
-#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
-#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
-#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
-#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
-#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
-#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
-#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
-#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
-#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
-#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
-#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
-#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_EN1 register.
-//
-//*****************************************************************************
-#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_EN2 register.
-//
-//*****************************************************************************
-#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_EN3 register.
-//
-//*****************************************************************************
-#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_EN4 register.
-//
-//*****************************************************************************
-#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DIS0 register.
-//
-//*****************************************************************************
-#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable
-#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
-#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
-#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
-#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
-#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
-#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
-#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
-#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
-#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
-#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
-#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
-#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
-#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
-#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
-#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
-#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
-#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
-#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
-#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
-#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
-#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
-#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
-#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
-#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
-#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
-#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
-#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
-#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
-#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
-#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
-#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
-#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DIS1 register.
-//
-//*****************************************************************************
-#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DIS2 register.
-//
-//*****************************************************************************
-#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DIS3 register.
-//
-//*****************************************************************************
-#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DIS4 register.
-//
-//*****************************************************************************
-#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PEND0 register.
-//
-//*****************************************************************************
-#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending
-#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
-#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
-#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
-#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
-#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
-#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
-#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
-#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
-#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
-#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
-#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
-#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
-#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
-#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
-#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
-#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
-#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
-#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
-#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
-#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
-#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
-#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
-#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
-#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
-#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
-#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
-#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
-#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
-#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
-#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
-#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
-#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PEND1 register.
-//
-//*****************************************************************************
-#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PEND2 register.
-//
-//*****************************************************************************
-#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PEND3 register.
-//
-//*****************************************************************************
-#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PEND4 register.
-//
-//*****************************************************************************
-#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_UNPEND0 register.
-//
-//*****************************************************************************
-#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending
-#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
-#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
-#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
-#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
-#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
-#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
-#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
-#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
-#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
-#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
-#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
-#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
-#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
-#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
-#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
-#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
-#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
-#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
-#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
-#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
-#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
-#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
-#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
-#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
-#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
-#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
-#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
-#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
-#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
-#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
-#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
-#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_UNPEND1 register.
-//
-//*****************************************************************************
-#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending
-#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
-#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
-#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
-#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
-#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
-#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
-#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
-#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
-#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
-#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
-#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
-#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
-#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
-#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
-#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
-#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
-#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
-#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
-#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
-#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
-#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
-#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
-#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
-#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_UNPEND2 register.
-//
-//*****************************************************************************
-#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_UNPEND3 register.
-//
-//*****************************************************************************
-#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_UNPEND4 register.
-//
-//*****************************************************************************
-#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
-//
-//*****************************************************************************
-#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active
-#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
-#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
-#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
-#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
-#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
-#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
-#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
-#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
-#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
-#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
-#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
-#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
-#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
-#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
-#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
-#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
-#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
-#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
-#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
-#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
-#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
-#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
-#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
-#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
-#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
-#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
-#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
-#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
-#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
-#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
-#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
-#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
-//
-//*****************************************************************************
-#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
-//
-//*****************************************************************************
-#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
-//
-//*****************************************************************************
-#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_ACTIVE4 register.
-//
-//*****************************************************************************
-#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI0 register.
-//
-//*****************************************************************************
-#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask
-#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask
-#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask
-#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask
-#define NVIC_PRI0_INT3_S 29
-#define NVIC_PRI0_INT2_S 21
-#define NVIC_PRI0_INT1_S 13
-#define NVIC_PRI0_INT0_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI1 register.
-//
-//*****************************************************************************
-#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask
-#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask
-#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask
-#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask
-#define NVIC_PRI1_INT7_S 29
-#define NVIC_PRI1_INT6_S 21
-#define NVIC_PRI1_INT5_S 13
-#define NVIC_PRI1_INT4_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI2 register.
-//
-//*****************************************************************************
-#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask
-#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask
-#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask
-#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask
-#define NVIC_PRI2_INT11_S 29
-#define NVIC_PRI2_INT10_S 21
-#define NVIC_PRI2_INT9_S 13
-#define NVIC_PRI2_INT8_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI3 register.
-//
-//*****************************************************************************
-#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask
-#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask
-#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask
-#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask
-#define NVIC_PRI3_INT15_S 29
-#define NVIC_PRI3_INT14_S 21
-#define NVIC_PRI3_INT13_S 13
-#define NVIC_PRI3_INT12_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI4 register.
-//
-//*****************************************************************************
-#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask
-#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask
-#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask
-#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask
-#define NVIC_PRI4_INT19_S 29
-#define NVIC_PRI4_INT18_S 21
-#define NVIC_PRI4_INT17_S 13
-#define NVIC_PRI4_INT16_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI5 register.
-//
-//*****************************************************************************
-#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask
-#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask
-#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask
-#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask
-#define NVIC_PRI5_INT23_S 29
-#define NVIC_PRI5_INT22_S 21
-#define NVIC_PRI5_INT21_S 13
-#define NVIC_PRI5_INT20_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI6 register.
-//
-//*****************************************************************************
-#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask
-#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask
-#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask
-#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask
-#define NVIC_PRI6_INT27_S 29
-#define NVIC_PRI6_INT26_S 21
-#define NVIC_PRI6_INT25_S 13
-#define NVIC_PRI6_INT24_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI7 register.
-//
-//*****************************************************************************
-#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask
-#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask
-#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask
-#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask
-#define NVIC_PRI7_INT31_S 29
-#define NVIC_PRI7_INT30_S 21
-#define NVIC_PRI7_INT29_S 13
-#define NVIC_PRI7_INT28_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI8 register.
-//
-//*****************************************************************************
-#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask
-#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask
-#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask
-#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask
-#define NVIC_PRI8_INT35_S 29
-#define NVIC_PRI8_INT34_S 21
-#define NVIC_PRI8_INT33_S 13
-#define NVIC_PRI8_INT32_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI9 register.
-//
-//*****************************************************************************
-#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask
-#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask
-#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask
-#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask
-#define NVIC_PRI9_INT39_S 29
-#define NVIC_PRI9_INT38_S 21
-#define NVIC_PRI9_INT37_S 13
-#define NVIC_PRI9_INT36_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI10 register.
-//
-//*****************************************************************************
-#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask
-#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask
-#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask
-#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask
-#define NVIC_PRI10_INT43_S 29
-#define NVIC_PRI10_INT42_S 21
-#define NVIC_PRI10_INT41_S 13
-#define NVIC_PRI10_INT40_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI11 register.
-//
-//*****************************************************************************
-#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask
-#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask
-#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask
-#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask
-#define NVIC_PRI11_INT47_S 29
-#define NVIC_PRI11_INT46_S 21
-#define NVIC_PRI11_INT45_S 13
-#define NVIC_PRI11_INT44_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI12 register.
-//
-//*****************************************************************************
-#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask
-#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask
-#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask
-#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask
-#define NVIC_PRI12_INT51_S 29
-#define NVIC_PRI12_INT50_S 21
-#define NVIC_PRI12_INT49_S 13
-#define NVIC_PRI12_INT48_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI13 register.
-//
-//*****************************************************************************
-#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask
-#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask
-#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask
-#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask
-#define NVIC_PRI13_INT55_S 29
-#define NVIC_PRI13_INT54_S 21
-#define NVIC_PRI13_INT53_S 13
-#define NVIC_PRI13_INT52_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI14 register.
-//
-//*****************************************************************************
-#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask
-#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask
-#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask
-#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask
-#define NVIC_PRI14_INTD_S 29
-#define NVIC_PRI14_INTC_S 21
-#define NVIC_PRI14_INTB_S 13
-#define NVIC_PRI14_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI15 register.
-//
-//*****************************************************************************
-#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask
-#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask
-#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask
-#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask
-#define NVIC_PRI15_INTD_S 29
-#define NVIC_PRI15_INTC_S 21
-#define NVIC_PRI15_INTB_S 13
-#define NVIC_PRI15_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI16 register.
-//
-//*****************************************************************************
-#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask
-#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask
-#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask
-#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask
-#define NVIC_PRI16_INTD_S 29
-#define NVIC_PRI16_INTC_S 21
-#define NVIC_PRI16_INTB_S 13
-#define NVIC_PRI16_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI17 register.
-//
-//*****************************************************************************
-#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask
-#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask
-#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask
-#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask
-#define NVIC_PRI17_INTD_S 29
-#define NVIC_PRI17_INTC_S 21
-#define NVIC_PRI17_INTB_S 13
-#define NVIC_PRI17_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI18 register.
-//
-//*****************************************************************************
-#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask
-#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask
-#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask
-#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask
-#define NVIC_PRI18_INTD_S 29
-#define NVIC_PRI18_INTC_S 21
-#define NVIC_PRI18_INTB_S 13
-#define NVIC_PRI18_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI19 register.
-//
-//*****************************************************************************
-#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask
-#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask
-#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask
-#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask
-#define NVIC_PRI19_INTD_S 29
-#define NVIC_PRI19_INTC_S 21
-#define NVIC_PRI19_INTB_S 13
-#define NVIC_PRI19_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI20 register.
-//
-//*****************************************************************************
-#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask
-#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask
-#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask
-#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask
-#define NVIC_PRI20_INTD_S 29
-#define NVIC_PRI20_INTC_S 21
-#define NVIC_PRI20_INTB_S 13
-#define NVIC_PRI20_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI21 register.
-//
-//*****************************************************************************
-#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask
-#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask
-#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask
-#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask
-#define NVIC_PRI21_INTD_S 29
-#define NVIC_PRI21_INTC_S 21
-#define NVIC_PRI21_INTB_S 13
-#define NVIC_PRI21_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI22 register.
-//
-//*****************************************************************************
-#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask
-#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask
-#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask
-#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask
-#define NVIC_PRI22_INTD_S 29
-#define NVIC_PRI22_INTC_S 21
-#define NVIC_PRI22_INTB_S 13
-#define NVIC_PRI22_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI23 register.
-//
-//*****************************************************************************
-#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask
-#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask
-#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask
-#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask
-#define NVIC_PRI23_INTD_S 29
-#define NVIC_PRI23_INTC_S 21
-#define NVIC_PRI23_INTB_S 13
-#define NVIC_PRI23_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI24 register.
-//
-//*****************************************************************************
-#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask
-#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask
-#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask
-#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask
-#define NVIC_PRI24_INTD_S 29
-#define NVIC_PRI24_INTC_S 21
-#define NVIC_PRI24_INTB_S 13
-#define NVIC_PRI24_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI25 register.
-//
-//*****************************************************************************
-#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask
-#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask
-#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask
-#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask
-#define NVIC_PRI25_INTD_S 29
-#define NVIC_PRI25_INTC_S 21
-#define NVIC_PRI25_INTB_S 13
-#define NVIC_PRI25_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI26 register.
-//
-//*****************************************************************************
-#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask
-#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask
-#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask
-#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask
-#define NVIC_PRI26_INTD_S 29
-#define NVIC_PRI26_INTC_S 21
-#define NVIC_PRI26_INTB_S 13
-#define NVIC_PRI26_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI27 register.
-//
-//*****************************************************************************
-#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask
-#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask
-#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask
-#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask
-#define NVIC_PRI27_INTD_S 29
-#define NVIC_PRI27_INTC_S 21
-#define NVIC_PRI27_INTB_S 13
-#define NVIC_PRI27_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI28 register.
-//
-//*****************************************************************************
-#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask
-#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask
-#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask
-#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask
-#define NVIC_PRI28_INTD_S 29
-#define NVIC_PRI28_INTC_S 21
-#define NVIC_PRI28_INTB_S 13
-#define NVIC_PRI28_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI29 register.
-//
-//*****************************************************************************
-#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask
-#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask
-#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask
-#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask
-#define NVIC_PRI29_INTD_S 29
-#define NVIC_PRI29_INTC_S 21
-#define NVIC_PRI29_INTB_S 13
-#define NVIC_PRI29_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI30 register.
-//
-//*****************************************************************************
-#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask
-#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask
-#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask
-#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask
-#define NVIC_PRI30_INTD_S 29
-#define NVIC_PRI30_INTC_S 21
-#define NVIC_PRI30_INTB_S 13
-#define NVIC_PRI30_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI31 register.
-//
-//*****************************************************************************
-#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask
-#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask
-#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask
-#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask
-#define NVIC_PRI31_INTD_S 29
-#define NVIC_PRI31_INTC_S 21
-#define NVIC_PRI31_INTB_S 13
-#define NVIC_PRI31_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI32 register.
-//
-//*****************************************************************************
-#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask
-#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask
-#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask
-#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask
-#define NVIC_PRI32_INTD_S 29
-#define NVIC_PRI32_INTC_S 21
-#define NVIC_PRI32_INTB_S 13
-#define NVIC_PRI32_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI33 register.
-//
-//*****************************************************************************
-#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
- // [4n+3]
-#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
- // [4n+2]
-#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
- // [4n+1]
-#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
- // [4n]
-#define NVIC_PRI33_INTD_S 29
-#define NVIC_PRI33_INTC_S 21
-#define NVIC_PRI33_INTB_S 13
-#define NVIC_PRI33_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_PRI34 register.
-//
-//*****************************************************************************
-#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
- // [4n+3]
-#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
- // [4n+2]
-#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
- // [4n+1]
-#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
- // [4n]
-#define NVIC_PRI34_INTD_S 29
-#define NVIC_PRI34_INTC_S 21
-#define NVIC_PRI34_INTB_S 13
-#define NVIC_PRI34_INTA_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_CPUID register.
-//
-//*****************************************************************************
-#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code
-#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM
-#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number
-#define NVIC_CPUID_CON_M 0x000F0000 // Constant
-#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number
-#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor
-#define NVIC_CPUID_REV_M 0x0000000F // Revision Number
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_INT_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending
-#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending
-#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending
-#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending
-#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending
-#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling
-#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending
-#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number
-#define NVIC_INT_CTRL_VEC_PEN_NMI \
- 0x00002000 // NMI
-#define NVIC_INT_CTRL_VEC_PEN_HARD \
- 0x00003000 // Hard fault
-#define NVIC_INT_CTRL_VEC_PEN_MEM \
- 0x00004000 // Memory management fault
-#define NVIC_INT_CTRL_VEC_PEN_BUS \
- 0x00005000 // Bus fault
-#define NVIC_INT_CTRL_VEC_PEN_USG \
- 0x00006000 // Usage fault
-#define NVIC_INT_CTRL_VEC_PEN_SVC \
- 0x0000B000 // SVCall
-#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
- 0x0000E000 // PendSV
-#define NVIC_INT_CTRL_VEC_PEN_TICK \
- 0x0000F000 // SysTick
-#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base
-#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number
-#define NVIC_INT_CTRL_VEC_ACT_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_VTABLE register.
-//
-//*****************************************************************************
-#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base
-#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset
-#define NVIC_VTABLE_OFFSET_S 10
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_APINT register.
-//
-//*****************************************************************************
-#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key
-#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
-#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess
-#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
-#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
-#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
-#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
-#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
-#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
-#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
-#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
-#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
-#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request
-#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault
-#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending
-#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable
-#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception
- // Entry
-#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and
- // Fault
-#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0
-#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access
-#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger
-#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
-//
-//*****************************************************************************
-#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority
-#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority
-#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority
-#define NVIC_SYS_PRI1_USAGE_S 21
-#define NVIC_SYS_PRI1_BUS_S 13
-#define NVIC_SYS_PRI1_MEM_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
-//
-//*****************************************************************************
-#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority
-#define NVIC_SYS_PRI2_SVC_S 29
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
-//
-//*****************************************************************************
-#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority
-#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority
-#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority
-#define NVIC_SYS_PRI3_TICK_S 29
-#define NVIC_SYS_PRI3_PENDSV_S 21
-#define NVIC_SYS_PRI3_DEBUG_S 5
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
-// register.
-//
-//*****************************************************************************
-#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable
-#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable
-#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable
-#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending
-#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending
-#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending
-#define NVIC_SYS_HND_CTRL_USAGEP \
- 0x00001000 // Usage Fault Pending
-#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active
-#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active
-#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active
-#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active
-#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active
-#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active
-#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_FAULT_STAT
-// register.
-//
-//*****************************************************************************
-#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault
-#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault
-#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault
-#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault
-#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault
-#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage
- // Fault
-#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
-#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy
- // State Preservation
-#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault
-#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault
-#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error
-#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error
-#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error
-#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address
- // Register Valid
-#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on
- // Floating-Point Lazy State
- // Preservation
-#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation
-#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation
-#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation
-#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_HFAULT_STAT
-// register.
-//
-//*****************************************************************************
-#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event
-#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault
-#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DEBUG_STAT
-// register.
-//
-//*****************************************************************************
-#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
-#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
-#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
-#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
-#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MM_ADDR register.
-//
-//*****************************************************************************
-#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address
-#define NVIC_MM_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_FAULT_ADDR
-// register.
-//
-//*****************************************************************************
-#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address
-#define NVIC_FAULT_ADDR_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_CPAC register.
-//
-//*****************************************************************************
-#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access
- // Privilege
-#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied
-#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only
-#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access
-#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access
- // Privilege
-#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied
-#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only
-#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
-//
-//*****************************************************************************
-#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions
-#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions
-#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU
-#define NVIC_MPU_TYPE_IREGION_S 16
-#define NVIC_MPU_TYPE_DREGION_S 8
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region
-#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults
-#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_NUMBER
-// register.
-//
-//*****************************************************************************
-#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access
-#define NVIC_MPU_NUMBER_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_BASE register.
-//
-//*****************************************************************************
-#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask
-#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid
-#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number
-#define NVIC_MPU_BASE_ADDR_S 5
-#define NVIC_MPU_BASE_REGION_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
-//
-//*****************************************************************************
-#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable
-#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege
-#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask
-#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
-#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
-#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
-#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits
-#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask
-#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
-//
-//*****************************************************************************
-#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask
-#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid
-#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number
-#define NVIC_MPU_BASE1_ADDR_S 5
-#define NVIC_MPU_BASE1_REGION_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
-//
-//*****************************************************************************
-#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable
-#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege
-#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask
-#define NVIC_MPU_ATTR1_SHAREABLE \
- 0x00040000 // Shareable
-#define NVIC_MPU_ATTR1_CACHEABLE \
- 0x00020000 // Cacheable
-#define NVIC_MPU_ATTR1_BUFFRABLE \
- 0x00010000 // Bufferable
-#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits
-#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask
-#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
-//
-//*****************************************************************************
-#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask
-#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid
-#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number
-#define NVIC_MPU_BASE2_ADDR_S 5
-#define NVIC_MPU_BASE2_REGION_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
-//
-//*****************************************************************************
-#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable
-#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege
-#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask
-#define NVIC_MPU_ATTR2_SHAREABLE \
- 0x00040000 // Shareable
-#define NVIC_MPU_ATTR2_CACHEABLE \
- 0x00020000 // Cacheable
-#define NVIC_MPU_ATTR2_BUFFRABLE \
- 0x00010000 // Bufferable
-#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits
-#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask
-#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
-//
-//*****************************************************************************
-#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask
-#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid
-#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number
-#define NVIC_MPU_BASE3_ADDR_S 5
-#define NVIC_MPU_BASE3_REGION_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
-//
-//*****************************************************************************
-#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable
-#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege
-#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask
-#define NVIC_MPU_ATTR3_SHAREABLE \
- 0x00040000 // Shareable
-#define NVIC_MPU_ATTR3_CACHEABLE \
- 0x00020000 // Cacheable
-#define NVIC_MPU_ATTR3_BUFFRABLE \
- 0x00010000 // Bufferable
-#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits
-#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask
-#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
-//
-//*****************************************************************************
-#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
-#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
-#define NVIC_DBG_CTRL_S_RESET_ST \
- 0x02000000 // Core has reset since last read
-#define NVIC_DBG_CTRL_S_RETIRE_ST \
- 0x01000000 // Core has executed insruction
- // since last read
-#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
-#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
-#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
-#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
-#define NVIC_DBG_CTRL_C_SNAPSTALL \
- 0x00000020 // Breaks a stalled load/store
-#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
-#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
-#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
-#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DBG_XFER register.
-//
-//*****************************************************************************
-#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
-#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
-#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
-#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
-#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
-#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
-#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
-#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
-#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
-#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
-#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
-#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
-#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
-#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
-#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
-#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
-#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
-#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
-#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
-#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
-#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
-#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
-#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DBG_DATA register.
-//
-//*****************************************************************************
-#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
-#define NVIC_DBG_DATA_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_DBG_INT register.
-//
-//*****************************************************************************
-#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
-#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
-#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
-#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
-#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
-#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
-#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
-#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
-#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
-#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
-#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_SW_TRIG register.
-//
-//*****************************************************************************
-#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID
-#define NVIC_SW_TRIG_INTID_S 0
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_FPCC register.
-//
-//*****************************************************************************
-#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation
- // Enable
-#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable
-#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready
-#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready
-#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready
-#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready
-#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode
-#define NVIC_FPCC_USER 0x00000002 // User Privilege Level
-#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_FPCA register.
-//
-//*****************************************************************************
-#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address
-#define NVIC_FPCA_ADDRESS_S 3
-
-//*****************************************************************************
-//
-// The following are defines for the bit fields in the NVIC_FPDSC register.
-//
-//*****************************************************************************
-#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default
-#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default
-#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default
-#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default
-#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode
-#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP)
- // mode
-#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity
- // (RM) mode
-#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode
-
-//*****************************************************************************
-//
-// The following definitions are deprecated.
-//
-//*****************************************************************************
-#ifndef DEPRECATED
-
-//*****************************************************************************
-//
-// Deprecated defines for the EEPROM register offsets.
-//
-//*****************************************************************************
-#define EEPROM_EEPROMPP_R (*((volatile unsigned long *)0x400AFFC0))
-
-//*****************************************************************************
-//
-// Deprecated defines for the bit fields in the EEPROM_EEPROMPP register.
-//
-//*****************************************************************************
-#define EEPROM_EEPROMPP_SIZE_M 0x0000001F // EEPROM Size
-#define EEPROM_EEPROMPP_SIZE_S 0
-
-#endif
-
-#endif // __LM4F120H5QR_H__
diff --git a/lesson-06/tm4c123-iar/project.ewd b/lesson-06/tm4c123-iar/project.ewd
index 60712cf..88d8748 100644
--- a/lesson-06/tm4c123-iar/project.ewd
+++ b/lesson-06/tm4c123-iar/project.ewd
@@ -44,7 +44,7 @@
MemFile
- $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\LM4F120H5QR.ddf
+ $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf
RunToEnable
@@ -112,7 +112,7 @@
FlashLoadersV3
- $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashLM4FxxxHxx.board
+ $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashTC4_H6_o.board
OCImagesSuppressCheck1
@@ -1188,7 +1188,7 @@
CCSTLinkProbeList
1
- 0
+ 2
CCSTLinkTargetVccEnable
diff --git a/lesson-06/tm4c123-iar/project.ewp b/lesson-06/tm4c123-iar/project.ewp
index f6ed365..afe4ee9 100644
--- a/lesson-06/tm4c123-iar/project.ewp
+++ b/lesson-06/tm4c123-iar/project.ewp
@@ -16,19 +16,19 @@
1
BrowseInfoPath
- Debug\BrowseInfo
+ dbg
ExePath
- Debug\Exe
+ dbg
ObjPath
- Debug\Obj
+ dbg
ListPath
- Debug\List
+ dbg
GEndianMode
@@ -36,11 +36,11 @@
Input description
- Full formatting.
+ Full formatting, without multibyte support.
Output description
- Full formatting.
+ Full formatting, without multibyte support.
GOutputBinary
@@ -62,7 +62,7 @@
RTDescription
- Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
+ A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
OGProductVersion
@@ -74,7 +74,7 @@
OGChipSelectEditMenu
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
GenLowLevelInterface
@@ -99,7 +99,7 @@
GBECoreSlave
32
- 40
+ 39
OGUseCmsis
@@ -120,7 +120,7 @@
GFPUDeviceSlave
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
FPU2
@@ -201,7 +201,7 @@
BuildFilesPath
- Debug
+ dbg
PointerAuthentication
@@ -287,7 +287,7 @@
CCAllowList
1
- 11111110
+ 10010100
CCDebugInfo
@@ -363,7 +363,7 @@
CCOptLevel
- 3
+ 2
CCOptStrategy
@@ -372,7 +372,7 @@
CCOptLevelSlave
- 3
+ 2
CCPosIndRopi
@@ -637,7 +637,7 @@
OOCOutputFormat
3
- 0
+ 3
OCOutputOverride
@@ -645,7 +645,7 @@
OOCOutputFile
- c.srec
+ project.bin
OOCCommandLineProducer
@@ -653,7 +653,7 @@
OOCObjCopyEnable
- 0
+ 1
@@ -756,7 +756,7 @@
IlinkIcfFile
- $TOOLKIT_DIR$\config\linker\TexasInstruments\LM4F120H5QR.icf
+ $TOOLKIT_DIR$\config\linker\TexasInstruments\TM4C123GH6.icf
IlinkIcfFileSlave
@@ -1077,9 +1077,9 @@
- $PROJ_DIR$\lm4f120h5qr.h
+ $PROJ_DIR$\main.c
- $PROJ_DIR$\main.c
+ $PROJ_DIR$\tm4c.h
diff --git a/lesson-07/tm4c123-iar/project.ewd b/lesson-07/tm4c123-iar/project.ewd
index 60712cf..88d8748 100644
--- a/lesson-07/tm4c123-iar/project.ewd
+++ b/lesson-07/tm4c123-iar/project.ewd
@@ -44,7 +44,7 @@
MemFile
- $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\LM4F120H5QR.ddf
+ $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf
RunToEnable
@@ -112,7 +112,7 @@
FlashLoadersV3
- $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashLM4FxxxHxx.board
+ $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashTC4_H6_o.board
OCImagesSuppressCheck1
@@ -1188,7 +1188,7 @@
CCSTLinkProbeList
1
- 0
+ 2
CCSTLinkTargetVccEnable
diff --git a/lesson-07/tm4c123-iar/project.ewp b/lesson-07/tm4c123-iar/project.ewp
index 43a0484..afe4ee9 100644
--- a/lesson-07/tm4c123-iar/project.ewp
+++ b/lesson-07/tm4c123-iar/project.ewp
@@ -16,19 +16,19 @@
1
BrowseInfoPath
- Debug\BrowseInfo
+ dbg
ExePath
- Debug\Exe
+ dbg
ObjPath
- Debug\Obj
+ dbg
ListPath
- Debug\List
+ dbg
GEndianMode
@@ -36,11 +36,11 @@
Input description
- Full formatting.
+ Full formatting, without multibyte support.
Output description
- Full formatting.
+ Full formatting, without multibyte support.
GOutputBinary
@@ -62,7 +62,7 @@
RTDescription
- Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
+ A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
OGProductVersion
@@ -74,7 +74,7 @@
OGChipSelectEditMenu
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
GenLowLevelInterface
@@ -99,7 +99,7 @@
GBECoreSlave
32
- 40
+ 39
OGUseCmsis
@@ -120,7 +120,7 @@
GFPUDeviceSlave
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
FPU2
@@ -201,7 +201,7 @@
BuildFilesPath
- Debug
+ dbg
PointerAuthentication
@@ -287,7 +287,7 @@
CCAllowList
1
- 11111110
+ 10010100
CCDebugInfo
@@ -363,7 +363,7 @@
CCOptLevel
- 3
+ 2
CCOptStrategy
@@ -372,7 +372,7 @@
CCOptLevelSlave
- 3
+ 2
CCPosIndRopi
@@ -637,7 +637,7 @@
OOCOutputFormat
3
- 0
+ 3
OCOutputOverride
@@ -645,7 +645,7 @@
OOCOutputFile
- c.srec
+ project.bin
OOCCommandLineProducer
@@ -653,7 +653,7 @@
OOCObjCopyEnable
- 0
+ 1
@@ -756,7 +756,7 @@
IlinkIcfFile
- $TOOLKIT_DIR$\config\linker\TexasInstruments\LM4F120H5QR.icf
+ $TOOLKIT_DIR$\config\linker\TexasInstruments\TM4C123GH6.icf
IlinkIcfFileSlave
diff --git a/lesson-08/tm4c123-iar/project.ewd b/lesson-08/tm4c123-iar/project.ewd
index 5598cf6..88d8748 100644
--- a/lesson-08/tm4c123-iar/project.ewd
+++ b/lesson-08/tm4c123-iar/project.ewd
@@ -44,7 +44,7 @@
MemFile
- $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\LM4F120H5QR.ddf
+ $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf
RunToEnable
@@ -112,7 +112,7 @@
FlashLoadersV3
- $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashLM4FxxxHxx.board
+ $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashTC4_H6_o.board
OCImagesSuppressCheck1
@@ -285,10 +285,6 @@
4
1
1
-
- CatchSFERR
- 1
-
OCDriverInfo
1
@@ -407,6 +403,10 @@
CatchINTERR
1
+
+ CatchSFERR
+ 1
+
CatchHARDERR
1
@@ -708,7 +708,7 @@
IjetTraceSizeList
0
- 2
+ 4
FlashBoardPathSlave
@@ -1188,7 +1188,7 @@
CCSTLinkProbeList
1
- 0
+ 2
CCSTLinkTargetVccEnable
@@ -1551,1554 +1551,4 @@
-
- Release
-
- ARM
-
- 0
-
- C-SPY
- 2
-
- 32
- 1
- 0
-
- CInput
- 1
-
-
- CEndian
- 1
-
-
- CProcessor
- 1
-
-
- OCVariant
- 0
-
-
- MacOverride
- 0
-
-
- MacFile
-
-
-
- MemOverride
- 0
-
-
- MemFile
-
-
-
- RunToEnable
- 1
-
-
- RunToName
- main
-
-
- CExtraOptionsCheck
- 0
-
-
- CExtraOptions
-
-
-
- CFpuProcessor
- 1
-
-
- OCDDFArgumentProducer
-
-
-
- OCDownloadSuppressDownload
- 0
-
-
- OCDownloadVerifyAll
- 0
-
-
- OCProductVersion
- 6.50.2.4581
-
-
- OCDynDriverList
- ARMSIM_ID
-
-
- OCLastSavedByProductVersion
-
-
-
- UseFlashLoader
- 0
-
-
- CLowLevel
- 1
-
-
- OCBE8Slave
- 1
-
-
- MacFile2
-
-
-
- CDevice
- 1
-
-
- FlashLoadersV3
-
-
-
- OCImagesSuppressCheck1
- 0
-
-
- OCImagesPath1
-
-
-
- OCImagesSuppressCheck2
- 0
-
-
- OCImagesPath2
-
-
-
- OCImagesSuppressCheck3
- 0
-
-
- OCImagesPath3
-
-
-
- OverrideDefFlashBoard
- 0
-
-
- OCImagesOffset1
-
-
-
- OCImagesOffset2
-
-
-
- OCImagesOffset3
-
-
-
- OCImagesUse1
- 0
-
-
- OCImagesUse2
- 0
-
-
- OCImagesUse3
- 0
-
-
- OCDeviceConfigMacroFile
- 1
-
-
- OCDebuggerExtraOption
- 1
-
-
- OCAllMTBOptions
- 1
-
-
- OCMulticoreNrOfCores
-
-
-
- OCMulticoreWorkspace
-
-
-
- OCMulticoreSlaveProject
-
-
-
- OCMulticoreSlaveConfiguration
-
-
-
- OCDownloadExtraImage
- 1
-
-
- OCAttachSlave
- 0
-
-
- MassEraseBeforeFlashing
- 0
-
-
- OCMulticoreNrOfCoresSlave
- 1
-
-
- OCMulticoreAMPConfigType
- 0
-
-
- OCMulticoreSessionFile
-
-
-
- OCTpiuBaseOption
- 1
-
-
-
-
- ARMSIM_ID
- 2
-
- 1
- 1
- 0
-
- OCSimDriverInfo
- 1
-
-
- OCSimEnablePSP
- 0
-
-
- OCSimPspOverrideConfig
- 0
-
-
- OCSimPspConfigFile
-
-
-
-
-
- CADI_ID
- 2
-
- 0
- 1
- 0
-
- CCadiMemory
- 1
-
-
- Fast Model
-
-
-
- CCADILogFileCheck
- 0
-
-
- CCADILogFileEditB
- $PROJ_DIR$\cspycomm.log
-
-
- OCDriverInfo
- 1
-
-
-
-
- CMSISDAP_ID
- 2
-
- 4
- 1
- 0
-
- CatchSFERR
- 1
-
-
- OCDriverInfo
- 1
-
-
- OCIarProbeScriptFile
- 1
-
-
- CMSISDAPResetList
- 1
- 10
-
-
- CMSISDAPHWResetDuration
- 300
-
-
- CMSISDAPHWResetDelay
- 200
-
-
- CMSISDAPDoLogfile
- 0
-
-
- CMSISDAPLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CMSISDAPInterfaceRadio
- 0
-
-
- CMSISDAPInterfaceCmdLine
- 0
-
-
- CMSISDAPMultiTargetEnable
- 0
-
-
- CMSISDAPMultiTarget
- 0
-
-
- CMSISDAPJtagSpeedList
- 0
- 0
-
-
- CMSISDAPBreakpointRadio
- 0
-
-
- CMSISDAPRestoreBreakpointsCheck
- 0
-
-
- CMSISDAPUpdateBreakpointsEdit
- _call_main
-
-
- RDICatchReset
- 0
-
-
- RDICatchUndef
- 1
-
-
- RDICatchSWI
- 0
-
-
- RDICatchData
- 1
-
-
- RDICatchPrefetch
- 1
-
-
- RDICatchIRQ
- 0
-
-
- RDICatchFIQ
- 0
-
-
- CatchCORERESET
- 0
-
-
- CatchMMERR
- 1
-
-
- CatchNOCPERR
- 1
-
-
- CatchCHKERR
- 1
-
-
- CatchSTATERR
- 1
-
-
- CatchBUSERR
- 1
-
-
- CatchINTERR
- 1
-
-
- CatchHARDERR
- 1
-
-
- CatchDummy
- 0
-
-
- CMSISDAPMultiCPUEnable
- 0
-
-
- CMSISDAPMultiCPUNumber
- 0
-
-
- OCProbeCfgOverride
- 0
-
-
- OCProbeConfig
-
-
-
- CMSISDAPProbeConfigRadio
- 0
-
-
- CMSISDAPSelectedCPUBehaviour
- 0
-
-
- ICpuName
-
-
-
- OCJetEmuParams
- 1
-
-
- CCCMSISDAPUsbSerialNo
-
-
-
- CCCMSISDAPUsbSerialNoSelect
- 0
-
-
-
-
- GDBSERVER_ID
- 2
-
- 0
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- TCPIP
- aaa.bbb.ccc.ddd
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCJTagBreakpointRadio
- 0
-
-
- CCJTagDoUpdateBreakpoints
- 0
-
-
- CCJTagUpdateBreakpoints
- _call_main
-
-
-
-
- IJET_ID
- 2
-
- 9
- 1
- 0
-
- CatchSFERR
- 1
-
-
- OCDriverInfo
- 1
-
-
- OCIarProbeScriptFile
- 1
-
-
- IjetResetList
- 1
- 10
-
-
- IjetHWResetDuration
- 300
-
-
- IjetHWResetDelay
- 200
-
-
- IjetPowerFromProbe
- 1
-
-
- IjetPowerRadio
- 0
-
-
- IjetDoLogfile
- 0
-
-
- IjetLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- IjetInterfaceRadio
- 0
-
-
- IjetInterfaceCmdLine
- 0
-
-
- IjetMultiTargetEnable
- 0
-
-
- IjetMultiTarget
- 0
-
-
- IjetScanChainNonARMDevices
- 0
-
-
- IjetIRLength
- 0
-
-
- IjetJtagSpeedList
- 0
- 0
-
-
- IjetProtocolRadio
- 0
-
-
- IjetSwoPin
- 0
-
-
- IjetCpuClockEdit
- 72.0
-
-
- IjetSwoPrescalerList
- 1
- 0
-
-
- IjetBreakpointRadio
- 0
-
-
- IjetRestoreBreakpointsCheck
- 0
-
-
- IjetUpdateBreakpointsEdit
- _call_main
-
-
- RDICatchReset
- 0
-
-
- RDICatchUndef
- 0
-
-
- RDICatchSWI
- 0
-
-
- RDICatchData
- 0
-
-
- RDICatchPrefetch
- 0
-
-
- RDICatchIRQ
- 0
-
-
- RDICatchFIQ
- 0
-
-
- CatchCORERESET
- 0
-
-
- CatchMMERR
- 0
-
-
- CatchNOCPERR
- 0
-
-
- CatchCHKERR
- 0
-
-
- CatchSTATERR
- 0
-
-
- CatchBUSERR
- 0
-
-
- CatchINTERR
- 0
-
-
- CatchHARDERR
- 0
-
-
- CatchDummy
- 0
-
-
- OCProbeCfgOverride
- 0
-
-
- OCProbeConfig
-
-
-
- IjetProbeConfigRadio
- 0
-
-
- IjetMultiCPUEnable
- 0
-
-
- IjetMultiCPUNumber
- 0
-
-
- IjetSelectedCPUBehaviour
- 0
-
-
- ICpuName
-
-
-
- OCJetEmuParams
- 1
-
-
- IjetPreferETB
- 1
-
-
- IjetTraceSettingsList
- 0
- 0
-
-
- IjetTraceSizeList
- 0
- 2
-
-
- FlashBoardPathSlave
- 0
-
-
- CCIjetUsbSerialNo
-
-
-
- CCIjetUsbSerialNoSelect
- 0
-
-
- CatchV8ARReset
- 0
-
-
- CatchV8AREREL1NS
- 0
-
-
- CatchV8AREREL1S
- 0
-
-
- CatchV8AREREL2NS
- 0
-
-
- CatchV8AREREL3S
- 0
-
-
- CatchV8AREEL1NS
- 0
-
-
- CatchV8ARREL1NS
- 0
-
-
- CatchV8AREEL1S
- 0
-
-
- CatchV8ARREL1S
- 0
-
-
- CatchV8AREEL2NS
- 0
-
-
- CatchV8ARREL2NS
- 0
-
-
- CatchV8AREEL3S
- 0
-
-
- CatchV8ARREL3S
- 0
-
-
-
-
- JLINK_ID
- 2
-
- 16
- 1
- 0
-
- CCCatchSFERR
- 0
-
-
- JLinkSpeed
- 32
-
-
- CCJLinkDoLogfile
- 0
-
-
- CCJLinkLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCJLinkHWResetDelay
- 0
-
-
- OCDriverInfo
- 1
-
-
- JLinkInitialSpeed
- 32
-
-
- CCDoJlinkMultiTarget
- 0
-
-
- CCScanChainNonARMDevices
- 0
-
-
- CCJLinkMultiTarget
- 0
-
-
- CCJLinkIRLength
- 0
-
-
- CCJLinkCommRadio
- 0
-
-
- CCJLinkTCPIP
- aaa.bbb.ccc.ddd
-
-
- CCJLinkSpeedRadioV2
- 0
-
-
- CCUSBDevice
- 1
- 1
-
-
- CCRDICatchReset
- 0
-
-
- CCRDICatchUndef
- 0
-
-
- CCRDICatchSWI
- 0
-
-
- CCRDICatchData
- 0
-
-
- CCRDICatchPrefetch
- 0
-
-
- CCRDICatchIRQ
- 0
-
-
- CCRDICatchFIQ
- 0
-
-
- CCJLinkBreakpointRadio
- 0
-
-
- CCJLinkDoUpdateBreakpoints
- 0
-
-
- CCJLinkUpdateBreakpoints
- _call_main
-
-
- CCJLinkInterfaceRadio
- 0
-
-
- CCJLinkResetList
- 6
- 5
-
-
- CCJLinkInterfaceCmdLine
- 0
-
-
- CCCatchCORERESET
- 0
-
-
- CCCatchMMERR
- 0
-
-
- CCCatchNOCPERR
- 0
-
-
- CCCatchCHRERR
- 0
-
-
- CCCatchSTATERR
- 0
-
-
- CCCatchBUSERR
- 0
-
-
- CCCatchINTERR
- 0
-
-
- CCCatchHARDERR
- 0
-
-
- CCCatchDummy
- 0
-
-
- OCJLinkScriptFile
- 1
-
-
- CCJLinkUsbSerialNo
-
-
-
- CCTcpIpAlt
- 0
- 0
-
-
- CCJLinkTcpIpSerialNo
-
-
-
- CCCpuClockEdit
- 72.0
-
-
- CCSwoClockAuto
- 0
-
-
- CCSwoClockEdit
- 2000
-
-
- OCJLinkTraceSource
- 0
-
-
- OCJLinkTraceSourceDummy
- 0
-
-
- OCJLinkDeviceName
- 1
-
-
-
-
- LMIFTDI_ID
- 2
-
- 3
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- LmiftdiSpeed
- 500
-
-
- CCLmiftdiDoLogfile
- 0
-
-
- CCLmiftdiLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCLmiFtdiInterfaceRadio
- 0
-
-
- CCLmiFtdiInterfaceCmdLine
- 0
-
-
- CCLmiftdiUsbSerialNo
-
-
-
- CCLmiftdiUsbSerialNoSelect
- 0
-
-
- CCLmiftdiResetList
- 0
- 0
-
-
-
-
- NULINK_ID
- 2
-
- 0
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
-
-
- PEMICRO_ID
- 2
-
- 3
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- CCJPEMicroShowSettings
- 0
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
-
-
- STLINK_ID
- 2
-
- 8
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- CCSTLinkInterfaceRadio
- 0
-
-
- CCSTLinkInterfaceCmdLine
- 0
-
-
- CCSTLinkResetList
- 3
- 0
-
-
- CCCpuClockEdit
- 72.0
-
-
- CCSwoClockAuto
- 0
-
-
- CCSwoClockEdit
- 2000
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCSTLinkDoUpdateBreakpoints
- 0
-
-
- CCSTLinkUpdateBreakpoints
- _call_main
-
-
- CCSTLinkCatchCORERESET
- 0
-
-
- CCSTLinkCatchMMERR
- 0
-
-
- CCSTLinkCatchNOCPERR
- 0
-
-
- CCSTLinkCatchCHRERR
- 0
-
-
- CCSTLinkCatchSTATERR
- 0
-
-
- CCSTLinkCatchBUSERR
- 0
-
-
- CCSTLinkCatchINTERR
- 0
-
-
- CCSTLinkCatchSFERR
- 0
-
-
- CCSTLinkCatchHARDERR
- 0
-
-
- CCSTLinkCatchDummy
- 0
-
-
- CCSTLinkUsbSerialNo
-
-
-
- CCSTLinkUsbSerialNoSelect
- 0
-
-
- CCSTLinkJtagSpeedList
- 2
- 0
-
-
- CCSTLinkDAPNumber
-
-
-
- CCSTLinkDebugAccessPortRadio
- 0
-
-
- CCSTLinkUseServerSelect
- 0
-
-
- CCSTLinkProbeList
- 1
- 0
-
-
- CCSTLinkTargetVccEnable
- 1
-
-
- CCSTLinkTargetVoltage
- ###Uninitialized###
-
-
-
-
- THIRDPARTY_ID
- 2
-
- 0
- 1
- 0
-
- CThirdPartyDriverDll
- ###Uninitialized###
-
-
- CThirdPartyLogFileCheck
- 0
-
-
- CThirdPartyLogFileEditB
- $PROJ_DIR$\cspycomm.log
-
-
- OCDriverInfo
- 1
-
-
-
-
- TIFET_ID
- 2
-
- 1
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- CCMSPFetResetList
- 0
- 0
-
-
- CCMSPFetInterfaceRadio
- 0
-
-
- CCMSPFetInterfaceCmdLine
- 0
-
-
- CCMSPFetTargetVccTypeDefault
- 0
-
-
- CCMSPFetTargetVoltage
- ###Uninitialized###
-
-
- CCMSPFetVCCDefault
- 1
-
-
- CCMSPFetTargetSettlingtime
- 0
-
-
- CCMSPFetRadioJtagSpeedType
- 1
-
-
- CCMSPFetConnection
- 0
- 0
-
-
- CCMSPFetUsbComPort
- Automatic
-
-
- CCMSPFetAllowAccessToBSL
- 0
-
-
- CCMSPFetDoLogfile
- 0
-
-
- CCMSPFetLogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCMSPFetRadioEraseFlash
- 1
-
-
-
-
- XDS100_ID
- 2
-
- 9
- 1
- 0
-
- OCDriverInfo
- 1
-
-
- TIPackageOverride
- 0
-
-
- TIPackage
-
-
-
- BoardFile
-
-
-
- DoLogfile
- 0
-
-
- LogFile
- $PROJ_DIR$\cspycomm.log
-
-
- CCXds100BreakpointRadio
- 0
-
-
- CCXds100DoUpdateBreakpoints
- 0
-
-
- CCXds100UpdateBreakpoints
- _call_main
-
-
- CCXds100CatchReset
- 0
-
-
- CCXds100CatchUndef
- 0
-
-
- CCXds100CatchSWI
- 0
-
-
- CCXds100CatchData
- 0
-
-
- CCXds100CatchPrefetch
- 0
-
-
- CCXds100CatchIRQ
- 0
-
-
- CCXds100CatchFIQ
- 0
-
-
- CCXds100CatchCORERESET
- 0
-
-
- CCXds100CatchMMERR
- 0
-
-
- CCXds100CatchNOCPERR
- 0
-
-
- CCXds100CatchCHRERR
- 0
-
-
- CCXds100CatchSTATERR
- 0
-
-
- CCXds100CatchBUSERR
- 0
-
-
- CCXds100CatchINTERR
- 0
-
-
- CCXds100CatchSFERR
- 0
-
-
- CCXds100CatchHARDERR
- 0
-
-
- CCXds100CatchDummy
- 0
-
-
- CCXds100CpuClockEdit
-
-
-
- CCXds100SwoClockAuto
- 0
-
-
- CCXds100SwoClockEdit
- 1000
-
-
- CCXds100HWResetDelay
- 0
-
-
- CCXds100ResetList
- 1
- 0
-
-
- CCXds100UsbSerialNo
-
-
-
- CCXds100UsbSerialNoSelect
- 0
-
-
- CCXds100JtagSpeedList
- 0
- 0
-
-
- CCXds100InterfaceRadio
- 0
-
-
- CCXds100InterfaceCmdLine
- 0
-
-
- CCXds100ProbeList
- 0
- 0
-
-
- CCXds100SWOPortRadio
- 0
-
-
- CCXds100SWOPort
- 1
-
-
- CCXDSTargetVccEnable
- 0
-
-
- CCXDSTargetVoltage
- ###Uninitialized###
-
-
- OCXDSDigitalStatesConfigFile
- 1
-
-
- OCSelectedCoreName
- 1
-
-
-
-
-
- $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
- 0
-
-
- $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
- 0
-
-
- $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
- 0
-
-
- $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
- 0
-
-
- $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
- 0
-
-
-
diff --git a/lesson-08/tm4c123-iar/project.ewp b/lesson-08/tm4c123-iar/project.ewp
index 491ff31..afe4ee9 100644
--- a/lesson-08/tm4c123-iar/project.ewp
+++ b/lesson-08/tm4c123-iar/project.ewp
@@ -16,19 +16,19 @@
1
BrowseInfoPath
- Debug\BrowseInfo
+ dbg
ExePath
- Debug\Exe
+ dbg
ObjPath
- Debug\Obj
+ dbg
ListPath
- Debug\List
+ dbg
GEndianMode
@@ -62,7 +62,7 @@
RTDescription
- Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
+ A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
OGProductVersion
@@ -74,7 +74,7 @@
OGChipSelectEditMenu
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
GenLowLevelInterface
@@ -120,7 +120,7 @@
GFPUDeviceSlave
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
FPU2
@@ -201,7 +201,7 @@
BuildFilesPath
- Debug
+ dbg
PointerAuthentication
@@ -287,7 +287,7 @@
CCAllowList
1
- 00000000
+ 10010100
CCDebugInfo
@@ -303,11 +303,11 @@
IExtraOptionsCheck
- 1
+ 0
IExtraOptions
- --align_sp_on_irq
+
CCLangConformance
@@ -319,7 +319,7 @@
CCRequirePrototypes
- 1
+ 0
CCDiagWarnAreErr
@@ -363,7 +363,7 @@
CCOptLevel
- 1
+ 2
CCOptStrategy
@@ -372,7 +372,7 @@
CCOptLevelSlave
- 1
+ 2
CCPosIndRopi
@@ -637,7 +637,7 @@
OOCOutputFormat
3
- 0
+ 3
OCOutputOverride
@@ -645,7 +645,7 @@
OOCOutputFile
- c.srec
+ project.bin
OOCCommandLineProducer
@@ -653,7 +653,7 @@
OOCObjCopyEnable
- 0
+ 1
@@ -728,7 +728,7 @@
IlinkMapFile
- 1
+ 0
IlinkLogFile
@@ -756,7 +756,7 @@
IlinkIcfFile
- $TOOLKIT_DIR$/config/linker/TexasInstruments/LM4F120H5QR.icf
+ $TOOLKIT_DIR$\config\linker\TexasInstruments\TM4C123GH6.icf
IlinkIcfFileSlave
@@ -989,7 +989,7 @@
IlinkTrustzoneImportLibraryOut
- project_import_lib.o
+ ###Unitialized###
OILinkExtraOption
@@ -1076,1081 +1076,6 @@
-
- Release
-
- ARM
-
- 0
-
- General
- 3
-
- 35
- 1
- 0
-
- BrowseInfoPath
- Release\BrowseInfo
-
-
- ExePath
- Release\Exe
-
-
- ObjPath
- Release\Obj
-
-
- ListPath
- Release\List
-
-
- GEndianMode
- 0
-
-
- Input description
- Full formatting.
-
-
- Output description
- Full formatting.
-
-
- GOutputBinary
- 0
-
-
- OGCoreOrChip
- 0
-
-
- GRuntimeLibSelect
- 0
- 1
-
-
- GRuntimeLibSelectSlave
- 0
- 1
-
-
- RTDescription
- Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
-
-
- OGProductVersion
- 5.10.0.159
-
-
- OGLastSavedByProductVersion
- 8.20.2.14834
-
-
- OGChipSelectEditMenu
- default None
-
-
- GenLowLevelInterface
- 0
-
-
- GEndianModeBE
- 0
-
-
- OGBufferedTerminalOutput
- 0
-
-
- GenStdoutInterface
- 0
-
-
- RTConfigPath2
- $TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h
-
-
- GBECoreSlave
- 32
- 0
-
-
- OGUseCmsis
- 0
-
-
- OGUseCmsisDspLib
- 0
-
-
- GRuntimeLibThreads
- 0
-
-
- CoreVariant
- 32
- 0
-
-
- GFPUDeviceSlave
- default None
-
-
- FPU2
- 0
- 0
-
-
- NrRegs
- 0
- 0
-
-
- NEON
- 0
-
-
- GFPUCoreSlave2
- 32
- 0
-
-
- OGCMSISPackSelectDevice
-
-
- OgLibHeap
- 0
-
-
- OGLibAdditionalLocale
- 0
-
-
- OGPrintfVariant
- 0
- 1
-
-
- OGPrintfMultibyteSupport
- 0
-
-
- OGScanfVariant
- 0
- 1
-
-
- OGScanfMultibyteSupport
- 0
-
-
- GenLocaleTags
-
-
-
- GenLocaleDisplayOnly
-
-
-
- DSPExtension
- 0
-
-
- TrustZone
- 0
-
-
- TrustZoneModes
- 0
- 0
-
-
- OGAarch64Abi
- 0
-
-
- OG_32_64Device
- 0
-
-
- BuildFilesPath
- Release
-
-
- PointerAuthentication
- 0
-
-
- FPU64
- 1
-
-
-
-
- ICCARM
- 2
-
- 37
- 1
- 0
-
- CCOptimizationNoSizeConstraints
- 0
-
-
- CCDefines
- NDEBUG
-
-
- CCPreprocFile
- 0
-
-
- CCPreprocComments
- 0
-
-
- CCPreprocLine
- 0
-
-
- CCListCFile
- 0
-
-
- CCListCMnemonics
- 0
-
-
- CCListCMessages
- 0
-
-
- CCListAssFile
- 0
-
-
- CCListAssSource
- 0
-
-
- CCEnableRemarks
- 0
-
-
- CCDiagSuppress
-
-
-
- CCDiagRemark
-
-
-
- CCDiagWarning
-
-
-
- CCDiagError
-
-
-
- CCObjPrefix
- 1
-
-
- CCAllowList
- 1
- 11111110
-
-
- CCDebugInfo
- 0
-
-
- IEndianMode
- 1
-
-
- IProcessor
- 1
-
-
- IExtraOptionsCheck
- 0
-
-
- IExtraOptions
-
-
-
- CCLangConformance
- 0
-
-
- CCSignedPlainChar
- 1
-
-
- CCRequirePrototypes
- 0
-
-
- CCDiagWarnAreErr
- 0
-
-
- CCCompilerRuntimeInfo
- 0
-
-
- IFpuProcessor
- 1
-
-
- OutputFile
- $FILE_BNAME$.o
-
-
- CCLibConfigHeader
- 1
-
-
- PreInclude
-
-
-
- CCIncludePath2
-
-
-
- CCStdIncCheck
- 0
-
-
- CCCodeSection
- .text
-
-
- IProcessorMode2
- 1
-
-
- CCOptLevel
- 3
-
-
- CCOptStrategy
- 0
- 0
-
-
- CCOptLevelSlave
- 3
-
-
- CCPosIndRopi
- 0
-
-
- CCPosIndRwpi
- 0
-
-
- CCPosIndNoDynInit
- 0
-
-
- IccLang
- 0
-
-
- IccCDialect
- 1
-
-
- IccAllowVLA
- 0
-
-
- IccStaticDestr
- 1
-
-
- IccCppInlineSemantics
- 0
-
-
- IccCmsis
- 1
-
-
- IccFloatSemantics
- 0
-
-
- CCNoLiteralPool
- 0
-
-
- CCOptStrategySlave
- 0
- 0
-
-
- CCGuardCalls
- 1
-
-
- CCEncSource
- 0
-
-
- CCEncOutput
- 0
-
-
- CCEncOutputBom
- 1
-
-
- CCEncInput
- 0
-
-
- IccExceptions2
- 0
-
-
- IccRTTI2
- 0
-
-
- OICompilerExtraOption
- 1
-
-
- CCStackProtection
- 0
-
-
-
-
- AARM
- 2
-
- 11
- 1
- 0
-
- AObjPrefix
- 1
-
-
- AEndian
- 1
-
-
- ACaseSensitivity
- 1
-
-
- MacroChars
- 0
- 0
-
-
- AWarnEnable
- 0
-
-
- AWarnWhat
- 0
-
-
- AWarnOne
-
-
-
- AWarnRange1
-
-
-
- AWarnRange2
-
-
-
- ADebug
- 0
-
-
- AltRegisterNames
- 0
-
-
- ADefines
-
-
-
- AList
- 0
-
-
- AListHeader
- 1
-
-
- AListing
- 1
-
-
- Includes
- 0
-
-
- MacDefs
- 0
-
-
- MacExps
- 1
-
-
- MacExec
- 0
-
-
- OnlyAssed
- 0
-
-
- MultiLine
- 0
-
-
- PageLengthCheck
- 0
-
-
- PageLength
- 80
-
-
- TabSpacing
- 8
-
-
- AXRef
- 0
-
-
- AXRefDefines
- 0
-
-
- AXRefInternal
- 0
-
-
- AXRefDual
- 0
-
-
- AProcessor
- 1
-
-
- AFpuProcessor
- 1
-
-
- AOutputFile
- $FILE_BNAME$.o
-
-
- ALimitErrorsCheck
- 0
-
-
- ALimitErrorsEdit
- 100
-
-
- AIgnoreStdInclude
- 0
-
-
- AUserIncludes
-
-
-
- AExtraOptionsCheckV2
- 0
-
-
- AExtraOptionsV2
-
-
-
- AsmNoLiteralPool
- 0
-
-
- PreInclude
-
-
-
-
-
- OBJCOPY
- 0
-
- 1
- 1
- 0
-
- OOCOutputFormat
- 3
- 0
-
-
- OCOutputOverride
- 0
-
-
- OOCOutputFile
- c.srec
-
-
- OOCCommandLineProducer
- 1
-
-
- OOCObjCopyEnable
- 0
-
-
-
-
- CUSTOM
- 3
-
-
-
- 0
- inputOutputBased
-
-
-
- BUILDACTION
- 1
-
-
-
-
-
-
- ILINK
- 0
-
- 27
- 1
- 0
-
- IlinkOutputFile
- c.out
-
-
- IlinkLibIOConfig
- 1
-
-
- IlinkInputFileSlave
- 0
-
-
- IlinkDebugInfoEnable
- 1
-
-
- IlinkKeepSymbols
-
-
-
- IlinkRawBinaryFile
-
-
-
- IlinkRawBinarySymbol
-
-
-
- IlinkRawBinarySegment
-
-
-
- IlinkRawBinaryAlign
-
-
-
- IlinkDefines
-
-
-
- IlinkConfigDefines
-
-
-
- IlinkMapFile
- 0
-
-
- IlinkLogFile
- 0
-
-
- IlinkLogInitialization
- 0
-
-
- IlinkLogModule
- 0
-
-
- IlinkLogSection
- 0
-
-
- IlinkLogVeneer
- 0
-
-
- IlinkIcfOverride
- 0
-
-
- IlinkIcfFile
- $TOOLKIT_DIR$\CONFIG\generic.icf
-
-
- IlinkIcfFileSlave
-
-
-
- IlinkEnableRemarks
- 0
-
-
- IlinkSuppressDiags
-
-
-
- IlinkTreatAsRem
-
-
-
- IlinkTreatAsWarn
-
-
-
- IlinkTreatAsErr
-
-
-
- IlinkWarningsAreErrors
- 0
-
-
- IlinkUseExtraOptions
- 0
-
-
- IlinkExtraOptions
-
-
-
- IlinkLowLevelInterfaceSlave
- 1
-
-
- IlinkAutoLibEnable
- 1
-
-
- IlinkAdditionalLibs
-
-
-
- IlinkOverrideProgramEntryLabel
- 0
-
-
- IlinkProgramEntryLabelSelect
- 0
-
-
- IlinkProgramEntryLabel
-
-
-
- DoFill
- 0
-
-
- FillerByte
- 0xFF
-
-
- FillerStart
- 0x0
-
-
- FillerEnd
- 0x0
-
-
- CrcSize
- 0
- 1
-
-
- CrcAlign
- 1
-
-
- CrcPoly
- 0x11021
-
-
- CrcCompl
- 0
- 0
-
-
- CrcBitOrder
- 0
- 0
-
-
- CrcInitialValue
- 0x0
-
-
- DoCrc
- 0
-
-
- IlinkBE8Slave
- 1
-
-
- IlinkBufferedTerminalOutput
- 1
-
-
- IlinkStdoutInterfaceSlave
- 1
-
-
- CrcFullSize
- 0
-
-
- IlinkIElfToolPostProcess
- 0
-
-
- IlinkLogAutoLibSelect
- 0
-
-
- IlinkLogRedirSymbols
- 0
-
-
- IlinkLogUnusedFragments
- 0
-
-
- IlinkCrcReverseByteOrder
- 0
-
-
- IlinkCrcUseAsInput
- 1
-
-
- IlinkOptInline
- 1
-
-
- IlinkOptExceptionsAllow
- 1
-
-
- IlinkOptExceptionsForce
- 0
-
-
- IlinkCmsis
- 1
-
-
- IlinkOptMergeDuplSections
- 0
-
-
- IlinkOptUseVfe
- 1
-
-
- IlinkOptForceVfe
- 0
-
-
- IlinkStackAnalysisEnable
- 0
-
-
- IlinkStackControlFile
-
-
-
- IlinkStackCallGraphFile
-
-
-
- CrcAlgorithm
- 1
- 1
-
-
- CrcUnitSize
- 0
- 0
-
-
- IlinkThreadsSlave
- 1
-
-
- IlinkLogCallGraph
- 0
-
-
- IlinkIcfFile_AltDefault
-
-
-
- IlinkEncInput
- 0
-
-
- IlinkEncOutput
- 0
-
-
- IlinkEncOutputBom
- 1
-
-
- IlinkHeapSelect
- 1
-
-
- IlinkLocaleSelect
- 1
-
-
- IlinkTrustzoneImportLibraryOut
- ###Unitialized###
-
-
- OILinkExtraOption
- 1
-
-
- IlinkRawBinaryFile2
-
-
-
- IlinkRawBinarySymbol2
-
-
-
- IlinkRawBinarySegment2
-
-
-
- IlinkRawBinaryAlign2
-
-
-
- IlinkLogCrtRoutineSelection
- 0
-
-
- IlinkLogFragmentInfo
- 0
-
-
- IlinkLogInlining
- 0
-
-
- IlinkLogMerging
- 0
-
-
- IlinkDemangle
- 0
-
-
- IlinkWrapperFileEnable
- 0
-
-
- IlinkWrapperFile
-
-
-
- IlinkProcessor
- 1
-
-
- IlinkFpuProcessor
- 1
-
-
-
-
- IARCHIVE
- 0
-
- 0
- 1
- 0
-
- IarchiveInputs
-
-
-
- IarchiveOverride
- 0
-
-
- IarchiveOutput
- ###Unitialized###
-
-
-
-
- Coder
- 0
-
-
-
$PROJ_DIR$\main.c
diff --git a/lesson-09/tm4c123-iar/project.ewd b/lesson-09/tm4c123-iar/project.ewd
index 60712cf..88d8748 100644
--- a/lesson-09/tm4c123-iar/project.ewd
+++ b/lesson-09/tm4c123-iar/project.ewd
@@ -44,7 +44,7 @@
MemFile
- $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\LM4F120H5QR.ddf
+ $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf
RunToEnable
@@ -112,7 +112,7 @@
FlashLoadersV3
- $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashLM4FxxxHxx.board
+ $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashTC4_H6_o.board
OCImagesSuppressCheck1
@@ -1188,7 +1188,7 @@
CCSTLinkProbeList
1
- 0
+ 2
CCSTLinkTargetVccEnable
diff --git a/lesson-09/tm4c123-iar/project.ewp b/lesson-09/tm4c123-iar/project.ewp
index 1a127ee..dc09607 100644
--- a/lesson-09/tm4c123-iar/project.ewp
+++ b/lesson-09/tm4c123-iar/project.ewp
@@ -16,19 +16,19 @@
1
BrowseInfoPath
- Debug\BrowseInfo
+ dbg
ExePath
- Debug\Exe
+ dbg
ObjPath
- Debug\Obj
+ dbg
ListPath
- Debug\List
+ dbg
GEndianMode
@@ -36,11 +36,11 @@
Input description
- Full formatting.
+ Full formatting, without multibyte support.
Output description
- Full formatting.
+ Full formatting, without multibyte support.
GOutputBinary
@@ -62,7 +62,7 @@
RTDescription
- Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
+ A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
OGProductVersion
@@ -74,7 +74,7 @@
OGChipSelectEditMenu
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
GenLowLevelInterface
@@ -99,7 +99,7 @@
GBECoreSlave
32
- 40
+ 39
OGUseCmsis
@@ -120,7 +120,7 @@
GFPUDeviceSlave
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
FPU2
@@ -201,7 +201,7 @@
BuildFilesPath
- Debug
+ dbg
PointerAuthentication
@@ -287,7 +287,7 @@
CCAllowList
1
- 00000000
+ 10010100
CCDebugInfo
@@ -319,7 +319,7 @@
CCRequirePrototypes
- 1
+ 0
CCDiagWarnAreErr
@@ -363,7 +363,7 @@
CCOptLevel
- 1
+ 2
CCOptStrategy
@@ -372,7 +372,7 @@
CCOptLevelSlave
- 1
+ 2
CCPosIndRopi
@@ -637,7 +637,7 @@
OOCOutputFormat
3
- 0
+ 3
OCOutputOverride
@@ -645,7 +645,7 @@
OOCOutputFile
- c.srec
+ project.bin
OOCCommandLineProducer
@@ -653,7 +653,7 @@
OOCObjCopyEnable
- 0
+ 1
@@ -756,7 +756,7 @@
IlinkIcfFile
- $TOOLKIT_DIR$\config\linker\TexasInstruments\LM4F120H5QR.icf
+ $TOOLKIT_DIR$\config\linker\TexasInstruments\TM4C123GH6.icf
IlinkIcfFileSlave
@@ -1080,9 +1080,12 @@
$PROJ_DIR$\delay.c
- $PROJ_DIR$\lm4f120h5qr.h
+ $PROJ_DIR$\delay.h
$PROJ_DIR$\main.c
+
+ $PROJ_DIR$\tm4c.h
+
diff --git a/lesson-10/tm4c123-iar/project.ewd b/lesson-10/tm4c123-iar/project.ewd
index 60712cf..88d8748 100644
--- a/lesson-10/tm4c123-iar/project.ewd
+++ b/lesson-10/tm4c123-iar/project.ewd
@@ -44,7 +44,7 @@
MemFile
- $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\LM4F120H5QR.ddf
+ $TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf
RunToEnable
@@ -112,7 +112,7 @@
FlashLoadersV3
- $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashLM4FxxxHxx.board
+ $TOOLKIT_DIR$/config/flashloader/TexasInstruments/FlashTC4_H6_o.board
OCImagesSuppressCheck1
@@ -1188,7 +1188,7 @@
CCSTLinkProbeList
1
- 0
+ 2
CCSTLinkTargetVccEnable
diff --git a/lesson-10/tm4c123-iar/project.ewp b/lesson-10/tm4c123-iar/project.ewp
index 244fc78..dc09607 100644
--- a/lesson-10/tm4c123-iar/project.ewp
+++ b/lesson-10/tm4c123-iar/project.ewp
@@ -16,19 +16,19 @@
1
BrowseInfoPath
- Debug\BrowseInfo
+ dbg
ExePath
- Debug\Exe
+ dbg
ObjPath
- Debug\Obj
+ dbg
ListPath
- Debug\List
+ dbg
GEndianMode
@@ -74,7 +74,7 @@
OGChipSelectEditMenu
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
GenLowLevelInterface
@@ -120,7 +120,7 @@
GFPUDeviceSlave
- LM4F120H5QR TexasInstruments LM4F120H5QR
+ TM4C123GH6PM TexasInstruments TM4C123GH6PM
FPU2
@@ -201,7 +201,7 @@
BuildFilesPath
- Debug
+ dbg
PointerAuthentication
@@ -287,7 +287,7 @@
CCAllowList
1
- 00000000
+ 10010100
CCDebugInfo
@@ -319,7 +319,7 @@
CCRequirePrototypes
- 1
+ 0
CCDiagWarnAreErr
@@ -363,7 +363,7 @@
CCOptLevel
- 1
+ 2
CCOptStrategy
@@ -372,7 +372,7 @@
CCOptLevelSlave
- 1
+ 2
CCPosIndRopi
@@ -637,7 +637,7 @@
OOCOutputFormat
3
- 0
+ 3
OCOutputOverride
@@ -645,7 +645,7 @@
OOCOutputFile
- c.srec
+ project.bin
OOCCommandLineProducer
@@ -653,7 +653,7 @@
OOCObjCopyEnable
- 0
+ 1
@@ -752,11 +752,11 @@
IlinkIcfOverride
- 1
+ 0
IlinkIcfFile
- $PROJ_DIR$\project.icf
+ $TOOLKIT_DIR$\config\linker\TexasInstruments\TM4C123GH6.icf
IlinkIcfFileSlave
@@ -989,7 +989,7 @@
IlinkTrustzoneImportLibraryOut
- project_import_lib.o
+ ###Unitialized###
OILinkExtraOption
@@ -1079,7 +1079,13 @@
$PROJ_DIR$\delay.c
+
+ $PROJ_DIR$\delay.h
+
$PROJ_DIR$\main.c
+
+ $PROJ_DIR$\tm4c.h
+
diff --git a/lesson-11/simulator-arm-iar/project.ewd b/lesson-11/simulator-arm-iar/project.ewd
index 4ca1a9a..4acf28c 100644
--- a/lesson-11/simulator-arm-iar/project.ewd
+++ b/lesson-11/simulator-arm-iar/project.ewd
@@ -92,7 +92,7 @@
UseFlashLoader
- 0
+ 1
CLowLevel
@@ -285,10 +285,6 @@
4
1
1
-
- CatchSFERR
- 1
-
OCDriverInfo
1
@@ -407,6 +403,10 @@
CatchINTERR
1
+
+ CatchSFERR
+ 1
+
CatchHARDERR
1
@@ -708,7 +708,7 @@
IjetTraceSizeList
0
- 2
+ 4
FlashBoardPathSlave
@@ -1188,7 +1188,7 @@
CCSTLinkProbeList
1
- 0
+ 2
CCSTLinkTargetVccEnable
@@ -1303,10 +1303,6 @@
9
1
1
-
- CCXds100CatchSFERR
- 0
-
OCDriverInfo
1
@@ -1399,6 +1395,10 @@
CCXds100CatchINTERR
0
+
+ CCXds100CatchSFERR
+ 0
+
CCXds100CatchHARDERR
0
@@ -1409,7 +1409,7 @@
CCXds100CpuClockEdit
- 72.0
+
CCXds100SwoClockAuto
diff --git a/lesson-11/simulator-arm-iar/project.ewp b/lesson-11/simulator-arm-iar/project.ewp
index 504c301..dc09607 100644
--- a/lesson-11/simulator-arm-iar/project.ewp
+++ b/lesson-11/simulator-arm-iar/project.ewp
@@ -16,19 +16,19 @@
1
BrowseInfoPath
- Debug\BrowseInfo
+ dbg
ExePath
- Debug\Exe
+ dbg
ObjPath
- Debug\Obj
+ dbg
ListPath
- Debug\List
+ dbg
GEndianMode
@@ -36,11 +36,11 @@
Input description
- Full formatting.
+ Full formatting, without multibyte support.
Output description
- Full formatting.
+ Full formatting, without multibyte support.
GOutputBinary
@@ -62,7 +62,7 @@
RTDescription
- Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
+ A compact configuration of the C/C++14 runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.
OGProductVersion
@@ -201,7 +201,7 @@
BuildFilesPath
- Debug
+ dbg
PointerAuthentication
@@ -287,7 +287,7 @@
CCAllowList
1
- 00000000
+ 10010100
CCDebugInfo
@@ -319,7 +319,7 @@
CCRequirePrototypes
- 1
+ 0
CCDiagWarnAreErr
@@ -363,7 +363,7 @@
CCOptLevel
- 1
+ 2
CCOptStrategy
@@ -372,7 +372,7 @@
CCOptLevelSlave
- 1
+ 2
CCPosIndRopi
@@ -637,7 +637,7 @@
OOCOutputFormat
3
- 0
+ 3
OCOutputOverride
@@ -645,7 +645,7 @@
OOCOutputFile
- c.srec
+ project.bin
OOCCommandLineProducer
@@ -653,7 +653,7 @@
OOCObjCopyEnable
- 0
+ 1
@@ -752,11 +752,11 @@
IlinkIcfOverride
- 1
+ 0
IlinkIcfFile
- $PROJ_DIR$\project.icf
+ $TOOLKIT_DIR$\config\linker\TexasInstruments\TM4C123GH6.icf
IlinkIcfFileSlave
@@ -1079,6 +1079,9 @@
$PROJ_DIR$\delay.c
+
+ $PROJ_DIR$\delay.h
+
$PROJ_DIR$\main.c
diff --git a/lesson-17/ek-tm4c123gxl/TM4C123GH6PM.h b/lesson-17/ek-tm4c123gxl/TM4C123GH6PM.h
new file mode 100644
index 0000000..10fb586
--- /dev/null
+++ b/lesson-17/ek-tm4c123gxl/TM4C123GH6PM.h
@@ -0,0 +1,1830 @@
+/*****************************************************************************
+* Modified from the original as follows:
+* - defined TARGET_IS_BLIZZARD_RA1 for compatibility with the TI library
+* - in GPIOA_Type struct replaced first __I RESERVED0[255] with
+* __IO uint32_t DATA_Bits[255] to access the individual GPIOA bits.
+* - added options for the ARMCC v6 compiler (CLANG)
+*
+* Quantum Leaps on 2018-01-31
+* https://www.state-machine.com
+*****************************************************************************/
+
+/****************************************************************************************************//**
+ * @file TM4C123GH6PM.h
+ *
+ * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for
+ * TM4C123GH6PM from Texas Instruments.
+ *
+ * @version V12591
+ * @date 19. February 2014
+ *
+ * @note Generated with SVDConv V2.79v
+ * from CMSIS SVD File 'TM4C123GH6PM.svd.xml' Version 12591,
+ *
+ * @par
+ * Software License Agreement
+ *
+ * Texas Instruments (TI) is supplying this software for use solely and
+ * exclusively on TI's microcontroller products. The software is owned by
+ * TI and/or its suppliers, and is protected under applicable copyright
+ * laws. You may not combine this software with "viral" open-source
+ * software in order to form a larger program.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
+ * NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
+ * NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
+ * CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ *
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Texas Instruments
+ * @{
+ */
+
+/** @addtogroup TM4C123GH6PM
+ * @{
+ */
+
+#ifndef TM4C123GH6PM_H
+#define TM4C123GH6PM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum {
+/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */
+/* ------------------- TM4C123GH6PM Specific Interrupt Numbers ------------------ */
+ GPIOA_IRQn = 0, /*!< 0 GPIOA */
+ GPIOB_IRQn = 1, /*!< 1 GPIOB */
+ GPIOC_IRQn = 2, /*!< 2 GPIOC */
+ GPIOD_IRQn = 3, /*!< 3 GPIOD */
+ GPIOE_IRQn = 4, /*!< 4 GPIOE */
+ UART0_IRQn = 5, /*!< 5 UART0 */
+ UART1_IRQn = 6, /*!< 6 UART1 */
+ SSI0_IRQn = 7, /*!< 7 SSI0 */
+ I2C0_IRQn = 8, /*!< 8 I2C0 */
+ PWM0_FAULT_IRQn = 9, /*!< 9 PWM0_FAULT */
+ PWM0_0_IRQn = 10, /*!< 10 PWM0_0 */
+ PWM0_1_IRQn = 11, /*!< 11 PWM0_1 */
+ PWM0_2_IRQn = 12, /*!< 12 PWM0_2 */
+ QEI0_IRQn = 13, /*!< 13 QEI0 */
+ ADC0SS0_IRQn = 14, /*!< 14 ADC0SS0 */
+ ADC0SS1_IRQn = 15, /*!< 15 ADC0SS1 */
+ ADC0SS2_IRQn = 16, /*!< 16 ADC0SS2 */
+ ADC0SS3_IRQn = 17, /*!< 17 ADC0SS3 */
+ WATCHDOG0_IRQn = 18, /*!< 18 WATCHDOG0 */
+ TIMER0A_IRQn = 19, /*!< 19 TIMER0A */
+ TIMER0B_IRQn = 20, /*!< 20 TIMER0B */
+ TIMER1A_IRQn = 21, /*!< 21 TIMER1A */
+ TIMER1B_IRQn = 22, /*!< 22 TIMER1B */
+ TIMER2A_IRQn = 23, /*!< 23 TIMER2A */
+ TIMER2B_IRQn = 24, /*!< 24 TIMER2B */
+ COMP0_IRQn = 25, /*!< 25 COMP0 */
+ COMP1_IRQn = 26, /*!< 26 COMP1 */
+ SYSCTL_IRQn = 28, /*!< 28 SYSCTL */
+ FLASH_CTRL_IRQn = 29, /*!< 29 FLASH_CTRL */
+ GPIOF_IRQn = 30, /*!< 30 GPIOF */
+ UART2_IRQn = 33, /*!< 33 UART2 */
+ SSI1_IRQn = 34, /*!< 34 SSI1 */
+ TIMER3A_IRQn = 35, /*!< 35 TIMER3A */
+ TIMER3B_IRQn = 36, /*!< 36 TIMER3B */
+ I2C1_IRQn = 37, /*!< 37 I2C1 */
+ QEI1_IRQn = 38, /*!< 38 QEI1 */
+ CAN0_IRQn = 39, /*!< 39 CAN0 */
+ CAN1_IRQn = 40, /*!< 40 CAN1 */
+ HIB_IRQn = 43, /*!< 43 HIB */
+ USB0_IRQn = 44, /*!< 44 USB0 */
+ PWM0_3_IRQn = 45, /*!< 45 PWM0_3 */
+ UDMA_IRQn = 46, /*!< 46 UDMA */
+ UDMAERR_IRQn = 47, /*!< 47 UDMAERR */
+ ADC1SS0_IRQn = 48, /*!< 48 ADC1SS0 */
+ ADC1SS1_IRQn = 49, /*!< 49 ADC1SS1 */
+ ADC1SS2_IRQn = 50, /*!< 50 ADC1SS2 */
+ ADC1SS3_IRQn = 51, /*!< 51 ADC1SS3 */
+ SSI2_IRQn = 57, /*!< 57 SSI2 */
+ SSI3_IRQn = 58, /*!< 58 SSI3 */
+ UART3_IRQn = 59, /*!< 59 UART3 */
+ UART4_IRQn = 60, /*!< 60 UART4 */
+ UART5_IRQn = 61, /*!< 61 UART5 */
+ UART6_IRQn = 62, /*!< 62 UART6 */
+ UART7_IRQn = 63, /*!< 63 UART7 */
+ I2C2_IRQn = 68, /*!< 68 I2C2 */
+ I2C3_IRQn = 69, /*!< 69 I2C3 */
+ TIMER4A_IRQn = 70, /*!< 70 TIMER4A */
+ TIMER4B_IRQn = 71, /*!< 71 TIMER4B */
+ TIMER5A_IRQn = 92, /*!< 92 TIMER5A */
+ TIMER5B_IRQn = 93, /*!< 93 TIMER5B */
+ WTIMER0A_IRQn = 94, /*!< 94 WTIMER0A */
+ WTIMER0B_IRQn = 95, /*!< 95 WTIMER0B */
+ WTIMER1A_IRQn = 96, /*!< 96 WTIMER1A */
+ WTIMER1B_IRQn = 97, /*!< 97 WTIMER1B */
+ WTIMER2A_IRQn = 98, /*!< 98 WTIMER2A */
+ WTIMER2B_IRQn = 99, /*!< 99 WTIMER2B */
+ WTIMER3A_IRQn = 100, /*!< 100 WTIMER3A */
+ WTIMER3B_IRQn = 101, /*!< 101 WTIMER3B */
+ WTIMER4A_IRQn = 102, /*!< 102 WTIMER4A */
+ WTIMER4B_IRQn = 103, /*!< 103 WTIMER4B */
+ WTIMER5A_IRQn = 104, /*!< 104 WTIMER5A */
+ WTIMER5B_IRQn = 105, /*!< 105 WTIMER5B */
+ SYSEXC_IRQn = 106, /*!< 106 SYSEXC */
+ PWM1_0_IRQn = 134, /*!< 134 PWM1_0 */
+ PWM1_1_IRQn = 135, /*!< 135 PWM1_1 */
+ PWM1_2_IRQn = 136, /*!< 136 PWM1_2 */
+ PWM1_3_IRQn = 137, /*!< 137 PWM1_3 */
+ PWM1_FAULT_IRQn = 138 /*!< 138 PWM1_FAULT */
+} IRQn_Type;
+
+/*
+ * ===========================================================================
+ * ---------- Interrupt Handler Prototypes -----------------------------------
+ * ===========================================================================
+ */
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void HardFault_Handler(void);
+
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+void GPIOPortA_IRQHandler(void);
+void GPIOPortB_IRQHandler(void);
+void GPIOPortC_IRQHandler(void);
+void GPIOPortD_IRQHandler(void);
+void GPIOPortE_IRQHandler(void);
+void UART0_IRQHandler(void);
+void UART1_IRQHandler(void);
+void SSI0_IRQHandler(void);
+void I2C0_IRQHandler(void);
+void PWMFault_IRQHandler(void);
+void PWMGen0_IRQHandler(void);
+void PWMGen1_IRQHandler(void);
+void PWMGen2_IRQHandler(void);
+void QEI0_IRQHandler(void);
+void ADCSeq0_IRQHandler(void);
+void ADCSeq1_IRQHandler(void);
+void ADCSeq2_IRQHandler(void);
+void ADCSeq3_IRQHandler(void);
+void Watchdog_IRQHandler(void);
+void Timer0A_IRQHandler(void);
+void Timer0B_IRQHandler(void);
+void Timer1A_IRQHandler(void);
+void Timer1B_IRQHandler(void);
+void Timer2A_IRQHandler(void);
+void Timer2B_IRQHandler(void);
+void Comp0_IRQHandler(void);
+void Comp1_IRQHandler(void);
+void Comp2_IRQHandler(void);
+void SysCtrl_IRQHandler(void);
+void FlashCtrl_IRQHandler(void);
+void GPIOPortF_IRQHandler(void);
+void GPIOPortG_IRQHandler(void);
+void GPIOPortH_IRQHandler(void);
+void UART2_IRQHandler(void);
+void SSI1_IRQHandler(void);
+void Timer3A_IRQHandler(void);
+void Timer3B_IRQHandler(void);
+void I2C1_IRQHandler(void);
+void QEI1_IRQHandler(void);
+void CAN0_IRQHandler(void);
+void CAN1_IRQHandler(void);
+void CAN2_IRQHandler(void);
+void Hibernate_IRQHandler(void);
+void USB0_IRQHandler(void);
+void PWMGen3_IRQHandler(void);
+void uDMAST_IRQHandler(void);
+void uDMAError_IRQHandler(void);
+void ADC1Seq0_IRQHandler(void);
+void ADC1Seq1_IRQHandler(void);
+void ADC1Seq2_IRQHandler(void);
+void ADC1Seq3_IRQHandler(void);
+void I2S0_IRQHandler(void);
+void EBI0_IRQHandler(void);
+void GPIOPortJ_IRQHandler(void);
+void GPIOPortK_IRQHandler(void);
+void GPIOPortL_IRQHandler(void);
+void SSI2_IRQHandler(void);
+void SSI3_IRQHandler(void);
+void UART3_IRQHandler(void);
+void UART4_IRQHandler(void);
+void UART5_IRQHandler(void);
+void UART6_IRQHandler(void);
+void UART7_IRQHandler(void);
+void I2C2_IRQHandler(void);
+void I2C3_IRQHandler(void);
+void Timer4A_IRQHandler(void);
+void Timer4B_IRQHandler(void);
+void Timer5A_IRQHandler(void);
+void Timer5B_IRQHandler(void);
+void WideTimer0A_IRQHandler(void);
+void WideTimer0B_IRQHandler(void);
+void WideTimer1A_IRQHandler(void);
+void WideTimer1B_IRQHandler(void);
+void WideTimer2A_IRQHandler(void);
+void WideTimer2B_IRQHandler(void);
+void WideTimer3A_IRQHandler(void);
+void WideTimer3B_IRQHandler(void);
+void WideTimer4A_IRQHandler(void);
+void WideTimer4B_IRQHandler(void);
+void WideTimer5A_IRQHandler(void);
+void WideTimer5B_IRQHandler(void);
+void FPU_IRQHandler(void);
+void PECI0_IRQHandler(void);
+void LPC0_IRQHandler(void);
+void I2C4_IRQHandler(void);
+void I2C5_IRQHandler(void);
+void GPIOPortM_IRQHandler(void);
+void GPIOPortN_IRQHandler(void);
+void QEI2_IRQHandler(void);
+void Fan0_IRQHandler(void);
+void GPIOPortP0_IRQHandler(void);
+void GPIOPortP1_IRQHandler(void);
+void GPIOPortP2_IRQHandler(void);
+void GPIOPortP3_IRQHandler(void);
+void GPIOPortP4_IRQHandler(void);
+void GPIOPortP5_IRQHandler(void);
+void GPIOPortP6_IRQHandler(void);
+void GPIOPortP7_IRQHandler(void);
+void GPIOPortQ0_IRQHandler(void);
+void GPIOPortQ1_IRQHandler(void);
+void GPIOPortQ2_IRQHandler(void);
+void GPIOPortQ3_IRQHandler(void);
+void GPIOPortQ4_IRQHandler(void);
+void GPIOPortQ5_IRQHandler(void);
+void GPIOPortQ6_IRQHandler(void);
+void GPIOPortQ7_IRQHandler(void);
+void GPIOPortR_IRQHandler(void);
+void GPIOPortS_IRQHandler(void);
+void PWM1Gen0_IRQHandler(void);
+void PWM1Gen1_IRQHandler(void);
+void PWM1Gen2_IRQHandler(void);
+void PWM1Gen3_IRQHandler(void);
+void PWM1Fault_IRQHandler(void);
+
+
+/** @addtogroup Configuration_of_CMSIS
+ * @{
+ */
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
+#define __CM4_REV 0x0102 /*!< Cortex-M4 Core Revision */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+#define TARGET_IS_BLIZZARD_RA1 1 /*!< Class of device (for TI library) */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
+#include "system_TM4C123GH6PM.h" /*!< TM4C123GH6PM System */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ /* anonymous unions are enabled by default */
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+/* ================================================================================ */
+/* ================ WATCHDOG0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for WATCHDOG0 peripheral (WATCHDOG0)
+ */
+
+typedef struct { /*!< WATCHDOG0 Structure */
+ __IO uint32_t LOAD; /*!< Watchdog Load */
+ __IO uint32_t VALUE; /*!< Watchdog Value */
+ __IO uint32_t CTL; /*!< Watchdog Control */
+ __O uint32_t ICR; /*!< Watchdog Interrupt Clear */
+ __IO uint32_t RIS; /*!< Watchdog Raw Interrupt Status */
+ __IO uint32_t MIS; /*!< Watchdog Masked Interrupt Status */
+ __I uint32_t RESERVED0[256];
+ __IO uint32_t TEST; /*!< Watchdog Test */
+ __I uint32_t RESERVED1[505];
+ __IO uint32_t LOCK; /*!< Watchdog Lock */
+} WATCHDOG0_Type;
+
+
+/* ================================================================================ */
+/* ================ GPIOA ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for GPIOA peripheral (GPIOA)
+ */
+
+typedef struct { /*!< GPIOA Structure */
+ __IO uint32_t DATA_Bits[255]; /*!< GPIO bit combinations */
+ __IO uint32_t DATA; /*!< GPIO Data */
+ __IO uint32_t DIR; /*!< GPIO Direction */
+ __IO uint32_t IS; /*!< GPIO Interrupt Sense */
+ __IO uint32_t IBE; /*!< GPIO Interrupt Both Edges */
+ __IO uint32_t IEV; /*!< GPIO Interrupt Event */
+ __IO uint32_t IM; /*!< GPIO Interrupt Mask */
+ __IO uint32_t RIS; /*!< GPIO Raw Interrupt Status */
+ __IO uint32_t MIS; /*!< GPIO Masked Interrupt Status */
+ __O uint32_t ICR; /*!< GPIO Interrupt Clear */
+ __IO uint32_t AFSEL; /*!< GPIO Alternate Function Select */
+ __I uint32_t RESERVED1[55];
+ __IO uint32_t DR2R; /*!< GPIO 2-mA Drive Select */
+ __IO uint32_t DR4R; /*!< GPIO 4-mA Drive Select */
+ __IO uint32_t DR8R; /*!< GPIO 8-mA Drive Select */
+ __IO uint32_t ODR; /*!< GPIO Open Drain Select */
+ __IO uint32_t PUR; /*!< GPIO Pull-Up Select */
+ __IO uint32_t PDR; /*!< GPIO Pull-Down Select */
+ __IO uint32_t SLR; /*!< GPIO Slew Rate Control Select */
+ __IO uint32_t DEN; /*!< GPIO Digital Enable */
+ __IO uint32_t LOCK; /*!< GPIO Lock */
+ __I uint32_t CR; /*!< GPIO Commit */
+ __IO uint32_t AMSEL; /*!< GPIO Analog Mode Select */
+ __IO uint32_t PCTL; /*!< GPIO Port Control */
+ __IO uint32_t ADCCTL; /*!< GPIO ADC Control */
+ __IO uint32_t DMACTL; /*!< GPIO DMA Control */
+} GPIOA_Type;
+
+
+/* ================================================================================ */
+/* ================ SSI0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for SSI0 peripheral (SSI0)
+ */
+
+typedef struct { /*!< SSI0 Structure */
+ __IO uint32_t CR0; /*!< SSI Control 0 */
+ __IO uint32_t CR1; /*!< SSI Control 1 */
+ __IO uint32_t DR; /*!< SSI Data */
+ __IO uint32_t SR; /*!< SSI Status */
+ __IO uint32_t CPSR; /*!< SSI Clock Prescale */
+ __IO uint32_t IM; /*!< SSI Interrupt Mask */
+ __IO uint32_t RIS; /*!< SSI Raw Interrupt Status */
+ __IO uint32_t MIS; /*!< SSI Masked Interrupt Status */
+ __O uint32_t ICR; /*!< SSI Interrupt Clear */
+ __IO uint32_t DMACTL; /*!< SSI DMA Control */
+ __I uint32_t RESERVED0[1000];
+ __IO uint32_t CC; /*!< SSI Clock Configuration */
+} SSI0_Type;
+
+
+/* ================================================================================ */
+/* ================ UART0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for UART0 peripheral (UART0)
+ */
+
+typedef struct { /*!< UART0 Structure */
+ __IO uint32_t DR; /*!< UART Data */
+
+ union {
+ __IO uint32_t ECR_UART_ALT; /*!< UART Receive Status/Error Clear */
+ __IO uint32_t RSR; /*!< UART Receive Status/Error Clear */
+ };
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FR; /*!< UART Flag */
+ __I uint32_t RESERVED1;
+ __IO uint32_t ILPR; /*!< UART IrDA Low-Power Register */
+ __IO uint32_t IBRD; /*!< UART Integer Baud-Rate Divisor */
+ __IO uint32_t FBRD; /*!< UART Fractional Baud-Rate Divisor */
+ __IO uint32_t LCRH; /*!< UART Line Control */
+ __IO uint32_t CTL; /*!< UART Control */
+ __IO uint32_t IFLS; /*!< UART Interrupt FIFO Level Select */
+ __IO uint32_t IM; /*!< UART Interrupt Mask */
+ __IO uint32_t RIS; /*!< UART Raw Interrupt Status */
+ __IO uint32_t MIS; /*!< UART Masked Interrupt Status */
+ __O uint32_t ICR; /*!< UART Interrupt Clear */
+ __IO uint32_t DMACTL; /*!< UART DMA Control */
+ __I uint32_t RESERVED2[22];
+ __IO uint32_t _9BITADDR; /*!< UART 9-Bit Self Address */
+ __IO uint32_t _9BITAMASK; /*!< UART 9-Bit Self Address Mask */
+ __I uint32_t RESERVED3[965];
+ __IO uint32_t PP; /*!< UART Peripheral Properties */
+ __I uint32_t RESERVED4;
+ __IO uint32_t CC; /*!< UART Clock Configuration */
+} UART0_Type;
+
+
+/* ================================================================================ */
+/* ================ I2C0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for I2C0 peripheral (I2C0)
+ */
+
+typedef struct { /*!< I2C0 Structure */
+ __IO uint32_t MSA; /*!< I2C Master Slave Address */
+
+ union {
+ __IO uint32_t MCS_I2C0_ALT; /*!< I2C Master Control/Status */
+ __IO uint32_t MCS; /*!< I2C Master Control/Status */
+ };
+ __IO uint32_t MDR; /*!< I2C Master Data */
+ __IO uint32_t MTPR; /*!< I2C Master Timer Period */
+ __IO uint32_t MIMR; /*!< I2C Master Interrupt Mask */
+ __IO uint32_t MRIS; /*!< I2C Master Raw Interrupt Status */
+ __IO uint32_t MMIS; /*!< I2C Master Masked Interrupt Status */
+ __O uint32_t MICR; /*!< I2C Master Interrupt Clear */
+ __IO uint32_t MCR; /*!< I2C Master Configuration */
+ __IO uint32_t MCLKOCNT; /*!< I2C Master Clock Low Timeout Count */
+ __I uint32_t RESERVED0;
+ __IO uint32_t MBMON; /*!< I2C Master Bus Monitor */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t MCR2; /*!< I2C Master Configuration 2 */
+ __I uint32_t RESERVED2[497];
+ __IO uint32_t SOAR; /*!< I2C Slave Own Address */
+
+ union {
+ __IO uint32_t SCSR_I2C0_ALT; /*!< I2C Slave Control/Status */
+ __IO uint32_t SCSR; /*!< I2C Slave Control/Status */
+ };
+ __IO uint32_t SDR; /*!< I2C Slave Data */
+ __IO uint32_t SIMR; /*!< I2C Slave Interrupt Mask */
+ __IO uint32_t SRIS; /*!< I2C Slave Raw Interrupt Status */
+ __IO uint32_t SMIS; /*!< I2C Slave Masked Interrupt Status */
+ __O uint32_t SICR; /*!< I2C Slave Interrupt Clear */
+ __IO uint32_t SOAR2; /*!< I2C Slave Own Address 2 */
+ __IO uint32_t SACKCTL; /*!< I2C Slave ACK Control */
+ __I uint32_t RESERVED3[487];
+ __IO uint32_t PP; /*!< I2C Peripheral Properties */
+ __IO uint32_t PC; /*!< I2C Peripheral Configuration */
+} I2C0_Type;
+
+
+/* ================================================================================ */
+/* ================ PWM0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for PWM0 peripheral (PWM0)
+ */
+
+typedef struct { /*!< PWM0 Structure */
+ __IO uint32_t CTL; /*!< PWM Master Control */
+ __IO uint32_t SYNC; /*!< PWM Time Base Sync */
+ __IO uint32_t ENABLE; /*!< PWM Output Enable */
+ __IO uint32_t INVERT; /*!< PWM Output Inversion */
+ __IO uint32_t FAULT; /*!< PWM Output Fault */
+ __IO uint32_t INTEN; /*!< PWM Interrupt Enable */
+ __IO uint32_t RIS; /*!< PWM Raw Interrupt Status */
+ __IO uint32_t ISC; /*!< PWM Interrupt Status and Clear */
+ __IO uint32_t STATUS; /*!< PWM Status */
+ __IO uint32_t FAULTVAL; /*!< PWM Fault Condition Value */
+ __IO uint32_t ENUPD; /*!< PWM Enable Update */
+ __I uint32_t RESERVED0[5];
+ __IO uint32_t _0_CTL; /*!< PWM0 Control */
+ __IO uint32_t _0_INTEN; /*!< PWM0 Interrupt and Trigger Enable */
+ __IO uint32_t _0_RIS; /*!< PWM0 Raw Interrupt Status */
+ __IO uint32_t _0_ISC; /*!< PWM0 Interrupt Status and Clear */
+ __IO uint32_t _0_LOAD; /*!< PWM0 Load */
+ __IO uint32_t _0_COUNT; /*!< PWM0 Counter */
+ __IO uint32_t _0_CMPA; /*!< PWM0 Compare A */
+ __IO uint32_t _0_CMPB; /*!< PWM0 Compare B */
+ __IO uint32_t _0_GENA; /*!< PWM0 Generator A Control */
+ __IO uint32_t _0_GENB; /*!< PWM0 Generator B Control */
+ __IO uint32_t _0_DBCTL; /*!< PWM0 Dead-Band Control */
+ __IO uint32_t _0_DBRISE; /*!< PWM0 Dead-Band Rising-Edge Delay */
+ __IO uint32_t _0_DBFALL; /*!< PWM0 Dead-Band Falling-Edge-Delay */
+ __IO uint32_t _0_FLTSRC0; /*!< PWM0 Fault Source 0 */
+ __IO uint32_t _0_FLTSRC1; /*!< PWM0 Fault Source 1 */
+ __IO uint32_t _0_MINFLTPER; /*!< PWM0 Minimum Fault Period */
+ __IO uint32_t _1_CTL; /*!< PWM1 Control */
+ __IO uint32_t _1_INTEN; /*!< PWM1 Interrupt and Trigger Enable */
+ __IO uint32_t _1_RIS; /*!< PWM1 Raw Interrupt Status */
+ __IO uint32_t _1_ISC; /*!< PWM1 Interrupt Status and Clear */
+ __IO uint32_t _1_LOAD; /*!< PWM1 Load */
+ __IO uint32_t _1_COUNT; /*!< PWM1 Counter */
+ __IO uint32_t _1_CMPA; /*!< PWM1 Compare A */
+ __IO uint32_t _1_CMPB; /*!< PWM1 Compare B */
+ __IO uint32_t _1_GENA; /*!< PWM1 Generator A Control */
+ __IO uint32_t _1_GENB; /*!< PWM1 Generator B Control */
+ __IO uint32_t _1_DBCTL; /*!< PWM1 Dead-Band Control */
+ __IO uint32_t _1_DBRISE; /*!< PWM1 Dead-Band Rising-Edge Delay */
+ __IO uint32_t _1_DBFALL; /*!< PWM1 Dead-Band Falling-Edge-Delay */
+ __IO uint32_t _1_FLTSRC0; /*!< PWM1 Fault Source 0 */
+ __IO uint32_t _1_FLTSRC1; /*!< PWM1 Fault Source 1 */
+ __IO uint32_t _1_MINFLTPER; /*!< PWM1 Minimum Fault Period */
+ __IO uint32_t _2_CTL; /*!< PWM2 Control */
+ __IO uint32_t _2_INTEN; /*!< PWM2 Interrupt and Trigger Enable */
+ __IO uint32_t _2_RIS; /*!< PWM2 Raw Interrupt Status */
+ __IO uint32_t _2_ISC; /*!< PWM2 Interrupt Status and Clear */
+ __IO uint32_t _2_LOAD; /*!< PWM2 Load */
+ __IO uint32_t _2_COUNT; /*!< PWM2 Counter */
+ __IO uint32_t _2_CMPA; /*!< PWM2 Compare A */
+ __IO uint32_t _2_CMPB; /*!< PWM2 Compare B */
+ __IO uint32_t _2_GENA; /*!< PWM2 Generator A Control */
+ __IO uint32_t _2_GENB; /*!< PWM2 Generator B Control */
+ __IO uint32_t _2_DBCTL; /*!< PWM2 Dead-Band Control */
+ __IO uint32_t _2_DBRISE; /*!< PWM2 Dead-Band Rising-Edge Delay */
+ __IO uint32_t _2_DBFALL; /*!< PWM2 Dead-Band Falling-Edge-Delay */
+ __IO uint32_t _2_FLTSRC0; /*!< PWM2 Fault Source 0 */
+ __IO uint32_t _2_FLTSRC1; /*!< PWM2 Fault Source 1 */
+ __IO uint32_t _2_MINFLTPER; /*!< PWM2 Minimum Fault Period */
+ __IO uint32_t _3_CTL; /*!< PWM3 Control */
+ __IO uint32_t _3_INTEN; /*!< PWM3 Interrupt and Trigger Enable */
+ __IO uint32_t _3_RIS; /*!< PWM3 Raw Interrupt Status */
+ __IO uint32_t _3_ISC; /*!< PWM3 Interrupt Status and Clear */
+ __IO uint32_t _3_LOAD; /*!< PWM3 Load */
+ __IO uint32_t _3_COUNT; /*!< PWM3 Counter */
+ __IO uint32_t _3_CMPA; /*!< PWM3 Compare A */
+ __IO uint32_t _3_CMPB; /*!< PWM3 Compare B */
+ __IO uint32_t _3_GENA; /*!< PWM3 Generator A Control */
+ __IO uint32_t _3_GENB; /*!< PWM3 Generator B Control */
+ __IO uint32_t _3_DBCTL; /*!< PWM3 Dead-Band Control */
+ __IO uint32_t _3_DBRISE; /*!< PWM3 Dead-Band Rising-Edge Delay */
+ __IO uint32_t _3_DBFALL; /*!< PWM3 Dead-Band Falling-Edge-Delay */
+ __IO uint32_t _3_FLTSRC0; /*!< PWM3 Fault Source 0 */
+ __IO uint32_t _3_FLTSRC1; /*!< PWM3 Fault Source 1 */
+ __IO uint32_t _3_MINFLTPER; /*!< PWM3 Minimum Fault Period */
+ __I uint32_t RESERVED1[432];
+ __IO uint32_t _0_FLTSEN; /*!< PWM0 Fault Pin Logic Sense */
+ __I uint32_t _0_FLTSTAT0; /*!< PWM0 Fault Status 0 */
+ __I uint32_t _0_FLTSTAT1; /*!< PWM0 Fault Status 1 */
+ __I uint32_t RESERVED2[29];
+ __IO uint32_t _1_FLTSEN; /*!< PWM1 Fault Pin Logic Sense */
+ __I uint32_t _1_FLTSTAT0; /*!< PWM1 Fault Status 0 */
+ __I uint32_t _1_FLTSTAT1; /*!< PWM1 Fault Status 1 */
+ __I uint32_t RESERVED3[30];
+ __I uint32_t _2_FLTSTAT0; /*!< PWM2 Fault Status 0 */
+ __I uint32_t _2_FLTSTAT1; /*!< PWM2 Fault Status 1 */
+ __I uint32_t RESERVED4[30];
+ __I uint32_t _3_FLTSTAT0; /*!< PWM3 Fault Status 0 */
+ __I uint32_t _3_FLTSTAT1; /*!< PWM3 Fault Status 1 */
+ __I uint32_t RESERVED5[397];
+ __IO uint32_t PP; /*!< PWM Peripheral Properties */
+} PWM0_Type;
+
+
+/* ================================================================================ */
+/* ================ QEI0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for QEI0 peripheral (QEI0)
+ */
+
+typedef struct { /*!< QEI0 Structure */
+ __IO uint32_t CTL; /*!< QEI Control */
+ __IO uint32_t STAT; /*!< QEI Status */
+ __IO uint32_t POS; /*!< QEI Position */
+ __IO uint32_t MAXPOS; /*!< QEI Maximum Position */
+ __IO uint32_t LOAD; /*!< QEI Timer Load */
+ __IO uint32_t TIME; /*!< QEI Timer */
+ __IO uint32_t COUNT; /*!< QEI Velocity Counter */
+ __IO uint32_t SPEED; /*!< QEI Velocity */
+ __IO uint32_t INTEN; /*!< QEI Interrupt Enable */
+ __IO uint32_t RIS; /*!< QEI Raw Interrupt Status */
+ __IO uint32_t ISC; /*!< QEI Interrupt Status and Clear */
+} QEI0_Type;
+
+
+/* ================================================================================ */
+/* ================ TIMER0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for TIMER0 peripheral (TIMER0)
+ */
+
+typedef struct { /*!< TIMER0 Structure */
+ __IO uint32_t CFG; /*!< GPTM Configuration */
+ __IO uint32_t TAMR; /*!< GPTM Timer A Mode */
+ __IO uint32_t TBMR; /*!< GPTM Timer B Mode */
+ __IO uint32_t CTL; /*!< GPTM Control */
+ __IO uint32_t SYNC; /*!< GPTM Synchronize */
+ __I uint32_t RESERVED0;
+ __IO uint32_t IMR; /*!< GPTM Interrupt Mask */
+ __IO uint32_t RIS; /*!< GPTM Raw Interrupt Status */
+ __IO uint32_t MIS; /*!< GPTM Masked Interrupt Status */
+ __O uint32_t ICR; /*!< GPTM Interrupt Clear */
+ __IO uint32_t TAILR; /*!< GPTM Timer A Interval Load */
+ __IO uint32_t TBILR; /*!< GPTM Timer B Interval Load */
+ __IO uint32_t TAMATCHR; /*!< GPTM Timer A Match */
+ __IO uint32_t TBMATCHR; /*!< GPTM Timer B Match */
+ __IO uint32_t TAPR; /*!< GPTM Timer A Prescale */
+ __IO uint32_t TBPR; /*!< GPTM Timer B Prescale */
+ __IO uint32_t TAPMR; /*!< GPTM TimerA Prescale Match */
+ __IO uint32_t TBPMR; /*!< GPTM TimerB Prescale Match */
+ __IO uint32_t TAR; /*!< GPTM Timer A */
+ __IO uint32_t TBR; /*!< GPTM Timer B */
+ __IO uint32_t TAV; /*!< GPTM Timer A Value */
+ __IO uint32_t TBV; /*!< GPTM Timer B Value */
+ __IO uint32_t RTCPD; /*!< GPTM RTC Predivide */
+ __IO uint32_t TAPS; /*!< GPTM Timer A Prescale Snapshot */
+ __IO uint32_t TBPS; /*!< GPTM Timer B Prescale Snapshot */
+ __IO uint32_t TAPV; /*!< GPTM Timer A Prescale Value */
+ __IO uint32_t TBPV; /*!< GPTM Timer B Prescale Value */
+ __I uint32_t RESERVED1[981];
+ __IO uint32_t PP; /*!< GPTM Peripheral Properties */
+} TIMER0_Type;
+
+
+/* ================================================================================ */
+/* ================ WTIMER0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for WTIMER0 peripheral (WTIMER0)
+ */
+
+typedef struct { /*!< WTIMER0 Structure */
+ __IO uint32_t CFG; /*!< GPTM Configuration */
+ __IO uint32_t TAMR; /*!< GPTM Timer A Mode */
+ __IO uint32_t TBMR; /*!< GPTM Timer B Mode */
+ __IO uint32_t CTL; /*!< GPTM Control */
+ __IO uint32_t SYNC; /*!< GPTM Synchronize */
+ __I uint32_t RESERVED0;
+ __IO uint32_t IMR; /*!< GPTM Interrupt Mask */
+ __IO uint32_t RIS; /*!< GPTM Raw Interrupt Status */
+ __IO uint32_t MIS; /*!< GPTM Masked Interrupt Status */
+ __O uint32_t ICR; /*!< GPTM Interrupt Clear */
+ __IO uint32_t TAILR; /*!< GPTM Timer A Interval Load */
+ __IO uint32_t TBILR; /*!< GPTM Timer B Interval Load */
+ __IO uint32_t TAMATCHR; /*!< GPTM Timer A Match */
+ __IO uint32_t TBMATCHR; /*!< GPTM Timer B Match */
+ __IO uint32_t TAPR; /*!< GPTM Timer A Prescale */
+ __IO uint32_t TBPR; /*!< GPTM Timer B Prescale */
+ __IO uint32_t TAPMR; /*!< GPTM TimerA Prescale Match */
+ __IO uint32_t TBPMR; /*!< GPTM TimerB Prescale Match */
+ __IO uint32_t TAR; /*!< GPTM Timer A */
+ __IO uint32_t TBR; /*!< GPTM Timer B */
+ __IO uint32_t TAV; /*!< GPTM Timer A Value */
+ __IO uint32_t TBV; /*!< GPTM Timer B Value */
+ __IO uint32_t RTCPD; /*!< GPTM RTC Predivide */
+ __IO uint32_t TAPS; /*!< GPTM Timer A Prescale Snapshot */
+ __IO uint32_t TBPS; /*!< GPTM Timer B Prescale Snapshot */
+ __IO uint32_t TAPV; /*!< GPTM Timer A Prescale Value */
+ __IO uint32_t TBPV; /*!< GPTM Timer B Prescale Value */
+ __I uint32_t RESERVED1[981];
+ __IO uint32_t PP; /*!< GPTM Peripheral Properties */
+} WTIMER0_Type;
+
+
+/* ================================================================================ */
+/* ================ ADC0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for ADC0 peripheral (ADC0)
+ */
+
+typedef struct { /*!< ADC0 Structure */
+ __IO uint32_t ACTSS; /*!< ADC Active Sample Sequencer */
+ __IO uint32_t RIS; /*!< ADC Raw Interrupt Status */
+ __IO uint32_t IM; /*!< ADC Interrupt Mask */
+ __IO uint32_t ISC; /*!< ADC Interrupt Status and Clear */
+ __IO uint32_t OSTAT; /*!< ADC Overflow Status */
+ __IO uint32_t EMUX; /*!< ADC Event Multiplexer Select */
+ __IO uint32_t USTAT; /*!< ADC Underflow Status */
+ __IO uint32_t TSSEL; /*!< ADC Trigger Source Select */
+ __IO uint32_t SSPRI; /*!< ADC Sample Sequencer Priority */
+ __IO uint32_t SPC; /*!< ADC Sample Phase Control */
+ __IO uint32_t PSSI; /*!< ADC Processor Sample Sequence Initiate */
+ __I uint32_t RESERVED0;
+ __IO uint32_t SAC; /*!< ADC Sample Averaging Control */
+ __IO uint32_t DCISC; /*!< ADC Digital Comparator Interrupt Status and Clear */
+ __IO uint32_t CTL; /*!< ADC Control */
+ __I uint32_t RESERVED1;
+ __IO uint32_t SSMUX0; /*!< ADC Sample Sequence Input Multiplexer Select 0 */
+ __IO uint32_t SSCTL0; /*!< ADC Sample Sequence Control 0 */
+ __IO uint32_t SSFIFO0; /*!< ADC Sample Sequence Result FIFO 0 */
+ __IO uint32_t SSFSTAT0; /*!< ADC Sample Sequence FIFO 0 Status */
+ __IO uint32_t SSOP0; /*!< ADC Sample Sequence 0 Operation */
+ __IO uint32_t SSDC0; /*!< ADC Sample Sequence 0 Digital Comparator Select */
+ __I uint32_t RESERVED2[2];
+ __IO uint32_t SSMUX1; /*!< ADC Sample Sequence Input Multiplexer Select 1 */
+ __IO uint32_t SSCTL1; /*!< ADC Sample Sequence Control 1 */
+ __IO uint32_t SSFIFO1; /*!< ADC Sample Sequence Result FIFO 1 */
+ __IO uint32_t SSFSTAT1; /*!< ADC Sample Sequence FIFO 1 Status */
+ __IO uint32_t SSOP1; /*!< ADC Sample Sequence 1 Operation */
+ __IO uint32_t SSDC1; /*!< ADC Sample Sequence 1 Digital Comparator Select */
+ __I uint32_t RESERVED3[2];
+ __IO uint32_t SSMUX2; /*!< ADC Sample Sequence Input Multiplexer Select 2 */
+ __IO uint32_t SSCTL2; /*!< ADC Sample Sequence Control 2 */
+ __IO uint32_t SSFIFO2; /*!< ADC Sample Sequence Result FIFO 2 */
+ __IO uint32_t SSFSTAT2; /*!< ADC Sample Sequence FIFO 2 Status */
+ __IO uint32_t SSOP2; /*!< ADC Sample Sequence 2 Operation */
+ __IO uint32_t SSDC2; /*!< ADC Sample Sequence 2 Digital Comparator Select */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t SSMUX3; /*!< ADC Sample Sequence Input Multiplexer Select 3 */
+ __IO uint32_t SSCTL3; /*!< ADC Sample Sequence Control 3 */
+ __IO uint32_t SSFIFO3; /*!< ADC Sample Sequence Result FIFO 3 */
+ __IO uint32_t SSFSTAT3; /*!< ADC Sample Sequence FIFO 3 Status */
+ __IO uint32_t SSOP3; /*!< ADC Sample Sequence 3 Operation */
+ __IO uint32_t SSDC3; /*!< ADC Sample Sequence 3 Digital Comparator Select */
+ __I uint32_t RESERVED5[786];
+ __O uint32_t DCRIC; /*!< ADC Digital Comparator Reset Initial Conditions */
+ __I uint32_t RESERVED6[63];
+ __IO uint32_t DCCTL0; /*!< ADC Digital Comparator Control 0 */
+ __IO uint32_t DCCTL1; /*!< ADC Digital Comparator Control 1 */
+ __IO uint32_t DCCTL2; /*!< ADC Digital Comparator Control 2 */
+ __IO uint32_t DCCTL3; /*!< ADC Digital Comparator Control 3 */
+ __IO uint32_t DCCTL4; /*!< ADC Digital Comparator Control 4 */
+ __IO uint32_t DCCTL5; /*!< ADC Digital Comparator Control 5 */
+ __IO uint32_t DCCTL6; /*!< ADC Digital Comparator Control 6 */
+ __IO uint32_t DCCTL7; /*!< ADC Digital Comparator Control 7 */
+ __I uint32_t RESERVED7[8];
+ __IO uint32_t DCCMP0; /*!< ADC Digital Comparator Range 0 */
+ __IO uint32_t DCCMP1; /*!< ADC Digital Comparator Range 1 */
+ __IO uint32_t DCCMP2; /*!< ADC Digital Comparator Range 2 */
+ __IO uint32_t DCCMP3; /*!< ADC Digital Comparator Range 3 */
+ __IO uint32_t DCCMP4; /*!< ADC Digital Comparator Range 4 */
+ __IO uint32_t DCCMP5; /*!< ADC Digital Comparator Range 5 */
+ __IO uint32_t DCCMP6; /*!< ADC Digital Comparator Range 6 */
+ __IO uint32_t DCCMP7; /*!< ADC Digital Comparator Range 7 */
+ __I uint32_t RESERVED8[88];
+ __IO uint32_t PP; /*!< ADC Peripheral Properties */
+ __IO uint32_t PC; /*!< ADC Peripheral Configuration */
+ __IO uint32_t CC; /*!< ADC Clock Configuration */
+} ADC0_Type;
+
+
+/* ================================================================================ */
+/* ================ COMP ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for COMP peripheral (COMP)
+ */
+
+typedef struct { /*!< COMP Structure */
+ __IO uint32_t ACMIS; /*!< Analog Comparator Masked Interrupt Status */
+ __IO uint32_t ACRIS; /*!< Analog Comparator Raw Interrupt Status */
+ __IO uint32_t ACINTEN; /*!< Analog Comparator Interrupt Enable */
+ __I uint32_t RESERVED0;
+ __IO uint32_t ACREFCTL; /*!< Analog Comparator Reference Voltage Control */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t ACSTAT0; /*!< Analog Comparator Status 0 */
+ __IO uint32_t ACCTL0; /*!< Analog Comparator Control 0 */
+ __I uint32_t RESERVED2[6];
+ __IO uint32_t ACSTAT1; /*!< Analog Comparator Status 1 */
+ __IO uint32_t ACCTL1; /*!< Analog Comparator Control 1 */
+ __I uint32_t RESERVED3[990];
+ __IO uint32_t PP; /*!< Analog Comparator Peripheral Properties */
+} COMP_Type;
+
+
+/* ================================================================================ */
+/* ================ CAN0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for CAN0 peripheral (CAN0)
+ */
+
+typedef struct { /*!< CAN0 Structure */
+ __IO uint32_t CTL; /*!< CAN Control */
+ __IO uint32_t STS; /*!< CAN Status */
+ __IO uint32_t ERR; /*!< CAN Error Counter */
+ __IO uint32_t BIT; /*!< CAN Bit Timing */
+ __IO uint32_t INT; /*!< CAN Interrupt */
+ __IO uint32_t TST; /*!< CAN Test */
+ __IO uint32_t BRPE; /*!< CAN Baud Rate Prescaler Extension */
+ __I uint32_t RESERVED0;
+ __IO uint32_t IF1CRQ; /*!< CAN IF1 Command Request */
+
+ union {
+ __IO uint32_t IF1CMSK_CAN0_ALT; /*!< CAN IF1 Command Mask */
+ __IO uint32_t IF1CMSK; /*!< CAN IF1 Command Mask */
+ };
+ __IO uint32_t IF1MSK1; /*!< CAN IF1 Mask 1 */
+ __IO uint32_t IF1MSK2; /*!< CAN IF1 Mask 2 */
+ __IO uint32_t IF1ARB1; /*!< CAN IF1 Arbitration 1 */
+ __IO uint32_t IF1ARB2; /*!< CAN IF1 Arbitration 2 */
+ __IO uint32_t IF1MCTL; /*!< CAN IF1 Message Control */
+ __IO uint32_t IF1DA1; /*!< CAN IF1 Data A1 */
+ __IO uint32_t IF1DA2; /*!< CAN IF1 Data A2 */
+ __IO uint32_t IF1DB1; /*!< CAN IF1 Data B1 */
+ __IO uint32_t IF1DB2; /*!< CAN IF1 Data B2 */
+ __I uint32_t RESERVED1[13];
+ __IO uint32_t IF2CRQ; /*!< CAN IF2 Command Request */
+
+ union {
+ __IO uint32_t IF2CMSK_CAN0_ALT; /*!< CAN IF2 Command Mask */
+ __IO uint32_t IF2CMSK; /*!< CAN IF2 Command Mask */
+ };
+ __IO uint32_t IF2MSK1; /*!< CAN IF2 Mask 1 */
+ __IO uint32_t IF2MSK2; /*!< CAN IF2 Mask 2 */
+ __IO uint32_t IF2ARB1; /*!< CAN IF2 Arbitration 1 */
+ __IO uint32_t IF2ARB2; /*!< CAN IF2 Arbitration 2 */
+ __IO uint32_t IF2MCTL; /*!< CAN IF2 Message Control */
+ __IO uint32_t IF2DA1; /*!< CAN IF2 Data A1 */
+ __IO uint32_t IF2DA2; /*!< CAN IF2 Data A2 */
+ __IO uint32_t IF2DB1; /*!< CAN IF2 Data B1 */
+ __IO uint32_t IF2DB2; /*!< CAN IF2 Data B2 */
+ __I uint32_t RESERVED2[21];
+ __IO uint32_t TXRQ1; /*!< CAN Transmission Request 1 */
+ __IO uint32_t TXRQ2; /*!< CAN Transmission Request 2 */
+ __I uint32_t RESERVED3[6];
+ __IO uint32_t NWDA1; /*!< CAN New Data 1 */
+ __IO uint32_t NWDA2; /*!< CAN New Data 2 */
+ __I uint32_t RESERVED4[6];
+ __IO uint32_t MSG1INT; /*!< CAN Message 1 Interrupt Pending */
+ __IO uint32_t MSG2INT; /*!< CAN Message 2 Interrupt Pending */
+ __I uint32_t RESERVED5[6];
+ __IO uint32_t MSG1VAL; /*!< CAN Message 1 Valid */
+ __IO uint32_t MSG2VAL; /*!< CAN Message 2 Valid */
+} CAN0_Type;
+
+
+/* ================================================================================ */
+/* ================ USB0 ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for USB0 peripheral (USB0)
+ */
+
+typedef struct { /*!< USB0 Structure */
+ __IO uint8_t FADDR; /*!< USB Device Functional Address */
+ __IO uint8_t POWER; /*!< USB Power */
+ __IO uint16_t TXIS; /*!< USB Transmit Interrupt Status */
+ __IO uint16_t RXIS; /*!< USB Receive Interrupt Status */
+ __IO uint16_t TXIE; /*!< USB Transmit Interrupt Enable */
+ __IO uint16_t RXIE; /*!< USB Receive Interrupt Enable */
+
+ union {
+ __IO uint8_t IS_USB0_ALT; /*!< USB General Interrupt Status */
+ __IO uint8_t IS; /*!< USB General Interrupt Status */
+ };
+
+ union {
+ __IO uint8_t IE_USB0_ALT; /*!< USB Interrupt Enable */
+ __IO uint8_t IE; /*!< USB Interrupt Enable */
+ };
+ __IO uint16_t FRAME; /*!< USB Frame Value */
+ __IO uint8_t EPIDX; /*!< USB Endpoint Index */
+ __IO uint8_t TEST; /*!< USB Test Mode */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FIFO0; /*!< USB FIFO Endpoint 0 */
+ __IO uint32_t FIFO1; /*!< USB FIFO Endpoint 1 */
+ __IO uint32_t FIFO2; /*!< USB FIFO Endpoint 2 */
+ __IO uint32_t FIFO3; /*!< USB FIFO Endpoint 3 */
+ __IO uint32_t FIFO4; /*!< USB FIFO Endpoint 4 */
+ __IO uint32_t FIFO5; /*!< USB FIFO Endpoint 5 */
+ __IO uint32_t FIFO6; /*!< USB FIFO Endpoint 6 */
+ __IO uint32_t FIFO7; /*!< USB FIFO Endpoint 7 */
+ __I uint32_t RESERVED1[8];
+ __IO uint8_t DEVCTL; /*!< USB Device Control */
+ __I uint8_t RESERVED2[1];
+ __IO uint8_t TXFIFOSZ; /*!< USB Transmit Dynamic FIFO Sizing */
+ __IO uint8_t RXFIFOSZ; /*!< USB Receive Dynamic FIFO Sizing */
+ __IO uint16_t TXFIFOADD; /*!< USB Transmit FIFO Start Address */
+ __IO uint16_t RXFIFOADD; /*!< USB Receive FIFO Start Address */
+ __I uint32_t RESERVED3[4];
+ __I uint16_t RESERVED4;
+ __IO uint8_t CONTIM; /*!< USB Connect Timing */
+ __IO uint8_t VPLEN; /*!< USB OTG VBUS Pulse Timing */
+ __I uint8_t RESERVED5[1];
+ __IO uint8_t FSEOF; /*!< USB Full-Speed Last Transaction to End of Frame Timing */
+ __IO uint8_t LSEOF; /*!< USB Low-Speed Last Transaction to End of Frame Timing */
+ __I uint8_t RESERVED6[1];
+ __IO uint8_t TXFUNCADDR0; /*!< USB Transmit Functional Address Endpoint 0 */
+ __I uint8_t RESERVED7[1];
+ __IO uint8_t TXHUBADDR0; /*!< USB Transmit Hub Address Endpoint 0 */
+ __IO uint8_t TXHUBPORT0; /*!< USB Transmit Hub Port Endpoint 0 */
+ __I uint32_t RESERVED8;
+ __IO uint8_t TXFUNCADDR1; /*!< USB Transmit Functional Address Endpoint 1 */
+ __I uint8_t RESERVED9[1];
+ __IO uint8_t TXHUBADDR1; /*!< USB Transmit Hub Address Endpoint 1 */
+ __IO uint8_t TXHUBPORT1; /*!< USB Transmit Hub Port Endpoint 1 */
+ __IO uint8_t RXFUNCADDR1; /*!< USB Receive Functional Address Endpoint 1 */
+ __I uint8_t RESERVED10[1];
+ __IO uint8_t RXHUBADDR1; /*!< USB Receive Hub Address Endpoint 1 */
+ __IO uint8_t RXHUBPORT1; /*!< USB Receive Hub Port Endpoint 1 */
+ __IO uint8_t TXFUNCADDR2; /*!< USB Transmit Functional Address Endpoint 2 */
+ __I uint8_t RESERVED11[1];
+ __IO uint8_t TXHUBADDR2; /*!< USB Transmit Hub Address Endpoint 2 */
+ __IO uint8_t TXHUBPORT2; /*!< USB Transmit Hub Port Endpoint 2 */
+ __IO uint8_t RXFUNCADDR2; /*!< USB Receive Functional Address Endpoint 2 */
+ __I uint8_t RESERVED12[1];
+ __IO uint8_t RXHUBADDR2; /*!< USB Receive Hub Address Endpoint 2 */
+ __IO uint8_t RXHUBPORT2; /*!< USB Receive Hub Port Endpoint 2 */
+ __IO uint8_t TXFUNCADDR3; /*!< USB Transmit Functional Address Endpoint 3 */
+ __I uint8_t RESERVED13[1];
+ __IO uint8_t TXHUBADDR3; /*!< USB Transmit Hub Address Endpoint 3 */
+ __IO uint8_t TXHUBPORT3; /*!< USB Transmit Hub Port Endpoint 3 */
+ __IO uint8_t RXFUNCADDR3; /*!< USB Receive Functional Address Endpoint 3 */
+ __I uint8_t RESERVED14[1];
+ __IO uint8_t RXHUBADDR3; /*!< USB Receive Hub Address Endpoint 3 */
+ __IO uint8_t RXHUBPORT3; /*!< USB Receive Hub Port Endpoint 3 */
+ __IO uint8_t TXFUNCADDR4; /*!< USB Transmit Functional Address Endpoint 4 */
+ __I uint8_t RESERVED15[1];
+ __IO uint8_t TXHUBADDR4; /*!< USB Transmit Hub Address Endpoint 4 */
+ __IO uint8_t TXHUBPORT4; /*!< USB Transmit Hub Port Endpoint 4 */
+ __IO uint8_t RXFUNCADDR4; /*!< USB Receive Functional Address Endpoint 4 */
+ __I uint8_t RESERVED16[1];
+ __IO uint8_t RXHUBADDR4; /*!< USB Receive Hub Address Endpoint 4 */
+ __IO uint8_t RXHUBPORT4; /*!< USB Receive Hub Port Endpoint 4 */
+ __IO uint8_t TXFUNCADDR5; /*!< USB Transmit Functional Address Endpoint 5 */
+ __I uint8_t RESERVED17[1];
+ __IO uint8_t TXHUBADDR5; /*!< USB Transmit Hub Address Endpoint 5 */
+ __IO uint8_t TXHUBPORT5; /*!< USB Transmit Hub Port Endpoint 5 */
+ __IO uint8_t RXFUNCADDR5; /*!< USB Receive Functional Address Endpoint 5 */
+ __I uint8_t RESERVED18[1];
+ __IO uint8_t RXHUBADDR5; /*!< USB Receive Hub Address Endpoint 5 */
+ __IO uint8_t RXHUBPORT5; /*!< USB Receive Hub Port Endpoint 5 */
+ __IO uint8_t TXFUNCADDR6; /*!< USB Transmit Functional Address Endpoint 6 */
+ __I uint8_t RESERVED19[1];
+ __IO uint8_t TXHUBADDR6; /*!< USB Transmit Hub Address Endpoint 6 */
+ __IO uint8_t TXHUBPORT6; /*!< USB Transmit Hub Port Endpoint 6 */
+ __IO uint8_t RXFUNCADDR6; /*!< USB Receive Functional Address Endpoint 6 */
+ __I uint8_t RESERVED20[1];
+ __IO uint8_t RXHUBADDR6; /*!< USB Receive Hub Address Endpoint 6 */
+ __IO uint8_t RXHUBPORT6; /*!< USB Receive Hub Port Endpoint 6 */
+ __IO uint8_t TXFUNCADDR7; /*!< USB Transmit Functional Address Endpoint 7 */
+ __I uint8_t RESERVED21[1];
+ __IO uint8_t TXHUBADDR7; /*!< USB Transmit Hub Address Endpoint 7 */
+ __IO uint8_t TXHUBPORT7; /*!< USB Transmit Hub Port Endpoint 7 */
+ __IO uint8_t RXFUNCADDR7; /*!< USB Receive Functional Address Endpoint 7 */
+ __I uint8_t RESERVED22[1];
+ __IO uint8_t RXHUBADDR7; /*!< USB Receive Hub Address Endpoint 7 */
+ __IO uint8_t RXHUBPORT7; /*!< USB Receive Hub Port Endpoint 7 */
+ __I uint32_t RESERVED23[16];
+ __I uint16_t RESERVED24;
+
+ union {
+ __O uint8_t CSRL0_USB0_ALT; /*!< USB Control and Status Endpoint 0 Low */
+ __O uint8_t CSRL0; /*!< USB Control and Status Endpoint 0 Low */
+ };
+ __O uint8_t CSRH0; /*!< USB Control and Status Endpoint 0 High */
+ __I uint16_t RESERVED25[3];
+ __IO uint8_t COUNT0; /*!< USB Receive Byte Count Endpoint 0 */
+ __I uint8_t RESERVED26[1];
+ __IO uint8_t TYPE0; /*!< USB Type Endpoint 0 */
+ __IO uint8_t NAKLMT; /*!< USB NAK Limit */
+ __I uint32_t RESERVED27;
+ __IO uint16_t TXMAXP1; /*!< USB Maximum Transmit Data Endpoint 1 */
+
+ union {
+ __IO uint8_t TXCSRL1_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 1 Low */
+ __IO uint8_t TXCSRL1; /*!< USB Transmit Control and Status Endpoint 1 Low */
+ };
+ __IO uint8_t TXCSRH1; /*!< USB Transmit Control and Status Endpoint 1 High */
+ __IO uint16_t RXMAXP1; /*!< USB Maximum Receive Data Endpoint 1 */
+
+ union {
+ __IO uint8_t RXCSRL1_USB0_ALT; /*!< USB Receive Control and Status Endpoint 1 Low */
+ __IO uint8_t RXCSRL1; /*!< USB Receive Control and Status Endpoint 1 Low */
+ };
+
+ union {
+ __IO uint8_t RXCSRH1_USB0_ALT; /*!< USB Receive Control and Status Endpoint 1 High */
+ __IO uint8_t RXCSRH1; /*!< USB Receive Control and Status Endpoint 1 High */
+ };
+ __IO uint16_t RXCOUNT1; /*!< USB Receive Byte Count Endpoint 1 */
+ __IO uint8_t TXTYPE1; /*!< USB Host Transmit Configure Type Endpoint 1 */
+
+ union {
+ __IO uint8_t TXINTERVAL1_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 1 */
+ __IO uint8_t TXINTERVAL1; /*!< USB Host Transmit Interval Endpoint 1 */
+ };
+ __IO uint8_t RXTYPE1; /*!< USB Host Configure Receive Type Endpoint 1 */
+
+ union {
+ __IO uint8_t RXINTERVAL1_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 1 */
+ __IO uint8_t RXINTERVAL1; /*!< USB Host Receive Polling Interval Endpoint 1 */
+ };
+ __I uint16_t RESERVED28;
+ __IO uint16_t TXMAXP2; /*!< USB Maximum Transmit Data Endpoint 2 */
+
+ union {
+ __IO uint8_t TXCSRL2_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 2 Low */
+ __IO uint8_t TXCSRL2; /*!< USB Transmit Control and Status Endpoint 2 Low */
+ };
+ __IO uint8_t TXCSRH2; /*!< USB Transmit Control and Status Endpoint 2 High */
+ __IO uint16_t RXMAXP2; /*!< USB Maximum Receive Data Endpoint 2 */
+
+ union {
+ __IO uint8_t RXCSRL2_USB0_ALT; /*!< USB Receive Control and Status Endpoint 2 Low */
+ __IO uint8_t RXCSRL2; /*!< USB Receive Control and Status Endpoint 2 Low */
+ };
+
+ union {
+ __IO uint8_t RXCSRH2_USB0_ALT; /*!< USB Receive Control and Status Endpoint 2 High */
+ __IO uint8_t RXCSRH2; /*!< USB Receive Control and Status Endpoint 2 High */
+ };
+ __IO uint16_t RXCOUNT2; /*!< USB Receive Byte Count Endpoint 2 */
+ __IO uint8_t TXTYPE2; /*!< USB Host Transmit Configure Type Endpoint 2 */
+
+ union {
+ __IO uint8_t TXINTERVAL2_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 2 */
+ __IO uint8_t TXINTERVAL2; /*!< USB Host Transmit Interval Endpoint 2 */
+ };
+ __IO uint8_t RXTYPE2; /*!< USB Host Configure Receive Type Endpoint 2 */
+
+ union {
+ __IO uint8_t RXINTERVAL2_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 2 */
+ __IO uint8_t RXINTERVAL2; /*!< USB Host Receive Polling Interval Endpoint 2 */
+ };
+ __I uint16_t RESERVED29;
+ __IO uint16_t TXMAXP3; /*!< USB Maximum Transmit Data Endpoint 3 */
+
+ union {
+ __IO uint8_t TXCSRL3_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 3 Low */
+ __IO uint8_t TXCSRL3; /*!< USB Transmit Control and Status Endpoint 3 Low */
+ };
+ __IO uint8_t TXCSRH3; /*!< USB Transmit Control and Status Endpoint 3 High */
+ __IO uint16_t RXMAXP3; /*!< USB Maximum Receive Data Endpoint 3 */
+
+ union {
+ __IO uint8_t RXCSRL3_USB0_ALT; /*!< USB Receive Control and Status Endpoint 3 Low */
+ __IO uint8_t RXCSRL3; /*!< USB Receive Control and Status Endpoint 3 Low */
+ };
+
+ union {
+ __IO uint8_t RXCSRH3_USB0_ALT; /*!< USB Receive Control and Status Endpoint 3 High */
+ __IO uint8_t RXCSRH3; /*!< USB Receive Control and Status Endpoint 3 High */
+ };
+ __IO uint16_t RXCOUNT3; /*!< USB Receive Byte Count Endpoint 3 */
+ __IO uint8_t TXTYPE3; /*!< USB Host Transmit Configure Type Endpoint 3 */
+
+ union {
+ __IO uint8_t TXINTERVAL3_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 3 */
+ __IO uint8_t TXINTERVAL3; /*!< USB Host Transmit Interval Endpoint 3 */
+ };
+ __IO uint8_t RXTYPE3; /*!< USB Host Configure Receive Type Endpoint 3 */
+
+ union {
+ __IO uint8_t RXINTERVAL3_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 3 */
+ __IO uint8_t RXINTERVAL3; /*!< USB Host Receive Polling Interval Endpoint 3 */
+ };
+ __I uint16_t RESERVED30;
+ __IO uint16_t TXMAXP4; /*!< USB Maximum Transmit Data Endpoint 4 */
+
+ union {
+ __IO uint8_t TXCSRL4_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 4 Low */
+ __IO uint8_t TXCSRL4; /*!< USB Transmit Control and Status Endpoint 4 Low */
+ };
+ __IO uint8_t TXCSRH4; /*!< USB Transmit Control and Status Endpoint 4 High */
+ __IO uint16_t RXMAXP4; /*!< USB Maximum Receive Data Endpoint 4 */
+
+ union {
+ __IO uint8_t RXCSRL4_USB0_ALT; /*!< USB Receive Control and Status Endpoint 4 Low */
+ __IO uint8_t RXCSRL4; /*!< USB Receive Control and Status Endpoint 4 Low */
+ };
+
+ union {
+ __IO uint8_t RXCSRH4_USB0_ALT; /*!< USB Receive Control and Status Endpoint 4 High */
+ __IO uint8_t RXCSRH4; /*!< USB Receive Control and Status Endpoint 4 High */
+ };
+ __IO uint16_t RXCOUNT4; /*!< USB Receive Byte Count Endpoint 4 */
+ __IO uint8_t TXTYPE4; /*!< USB Host Transmit Configure Type Endpoint 4 */
+
+ union {
+ __IO uint8_t TXINTERVAL4_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 4 */
+ __IO uint8_t TXINTERVAL4; /*!< USB Host Transmit Interval Endpoint 4 */
+ };
+ __IO uint8_t RXTYPE4; /*!< USB Host Configure Receive Type Endpoint 4 */
+
+ union {
+ __IO uint8_t RXINTERVAL4_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 4 */
+ __IO uint8_t RXINTERVAL4; /*!< USB Host Receive Polling Interval Endpoint 4 */
+ };
+ __I uint16_t RESERVED31;
+ __IO uint16_t TXMAXP5; /*!< USB Maximum Transmit Data Endpoint 5 */
+
+ union {
+ __IO uint8_t TXCSRL5_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 5 Low */
+ __IO uint8_t TXCSRL5; /*!< USB Transmit Control and Status Endpoint 5 Low */
+ };
+ __IO uint8_t TXCSRH5; /*!< USB Transmit Control and Status Endpoint 5 High */
+ __IO uint16_t RXMAXP5; /*!< USB Maximum Receive Data Endpoint 5 */
+
+ union {
+ __IO uint8_t RXCSRL5_USB0_ALT; /*!< USB Receive Control and Status Endpoint 5 Low */
+ __IO uint8_t RXCSRL5; /*!< USB Receive Control and Status Endpoint 5 Low */
+ };
+
+ union {
+ __IO uint8_t RXCSRH5_USB0_ALT; /*!< USB Receive Control and Status Endpoint 5 High */
+ __IO uint8_t RXCSRH5; /*!< USB Receive Control and Status Endpoint 5 High */
+ };
+ __IO uint16_t RXCOUNT5; /*!< USB Receive Byte Count Endpoint 5 */
+ __IO uint8_t TXTYPE5; /*!< USB Host Transmit Configure Type Endpoint 5 */
+
+ union {
+ __IO uint8_t TXINTERVAL5_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 5 */
+ __IO uint8_t TXINTERVAL5; /*!< USB Host Transmit Interval Endpoint 5 */
+ };
+ __IO uint8_t RXTYPE5; /*!< USB Host Configure Receive Type Endpoint 5 */
+
+ union {
+ __IO uint8_t RXINTERVAL5_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 5 */
+ __IO uint8_t RXINTERVAL5; /*!< USB Host Receive Polling Interval Endpoint 5 */
+ };
+ __I uint16_t RESERVED32;
+ __IO uint16_t TXMAXP6; /*!< USB Maximum Transmit Data Endpoint 6 */
+
+ union {
+ __IO uint8_t TXCSRL6_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 6 Low */
+ __IO uint8_t TXCSRL6; /*!< USB Transmit Control and Status Endpoint 6 Low */
+ };
+ __IO uint8_t TXCSRH6; /*!< USB Transmit Control and Status Endpoint 6 High */
+ __IO uint16_t RXMAXP6; /*!< USB Maximum Receive Data Endpoint 6 */
+
+ union {
+ __IO uint8_t RXCSRL6_USB0_ALT; /*!< USB Receive Control and Status Endpoint 6 Low */
+ __IO uint8_t RXCSRL6; /*!< USB Receive Control and Status Endpoint 6 Low */
+ };
+
+ union {
+ __IO uint8_t RXCSRH6_USB0_ALT; /*!< USB Receive Control and Status Endpoint 6 High */
+ __IO uint8_t RXCSRH6; /*!< USB Receive Control and Status Endpoint 6 High */
+ };
+ __IO uint16_t RXCOUNT6; /*!< USB Receive Byte Count Endpoint 6 */
+ __IO uint8_t TXTYPE6; /*!< USB Host Transmit Configure Type Endpoint 6 */
+
+ union {
+ __IO uint8_t TXINTERVAL6_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 6 */
+ __IO uint8_t TXINTERVAL6; /*!< USB Host Transmit Interval Endpoint 6 */
+ };
+ __IO uint8_t RXTYPE6; /*!< USB Host Configure Receive Type Endpoint 6 */
+
+ union {
+ __IO uint8_t RXINTERVAL6_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 6 */
+ __IO uint8_t RXINTERVAL6; /*!< USB Host Receive Polling Interval Endpoint 6 */
+ };
+ __I uint16_t RESERVED33;
+ __IO uint16_t TXMAXP7; /*!< USB Maximum Transmit Data Endpoint 7 */
+
+ union {
+ __IO uint8_t TXCSRL7_USB0_ALT; /*!< USB Transmit Control and Status Endpoint 7 Low */
+ __IO uint8_t TXCSRL7; /*!< USB Transmit Control and Status Endpoint 7 Low */
+ };
+ __IO uint8_t TXCSRH7; /*!< USB Transmit Control and Status Endpoint 7 High */
+ __IO uint16_t RXMAXP7; /*!< USB Maximum Receive Data Endpoint 7 */
+
+ union {
+ __IO uint8_t RXCSRL7_USB0_ALT; /*!< USB Receive Control and Status Endpoint 7 Low */
+ __IO uint8_t RXCSRL7; /*!< USB Receive Control and Status Endpoint 7 Low */
+ };
+
+ union {
+ __IO uint8_t RXCSRH7_USB0_ALT; /*!< USB Receive Control and Status Endpoint 7 High */
+ __IO uint8_t RXCSRH7; /*!< USB Receive Control and Status Endpoint 7 High */
+ };
+ __IO uint16_t RXCOUNT7; /*!< USB Receive Byte Count Endpoint 7 */
+ __IO uint8_t TXTYPE7; /*!< USB Host Transmit Configure Type Endpoint 7 */
+
+ union {
+ __IO uint8_t TXINTERVAL7_USB0_ALT; /*!< USB Host Transmit Interval Endpoint 7 */
+ __IO uint8_t TXINTERVAL7; /*!< USB Host Transmit Interval Endpoint 7 */
+ };
+ __IO uint8_t RXTYPE7; /*!< USB Host Configure Receive Type Endpoint 7 */
+
+ union {
+ __IO uint8_t RXINTERVAL7_USB0_ALT; /*!< USB Host Receive Polling Interval Endpoint 7 */
+ __IO uint8_t RXINTERVAL7; /*!< USB Host Receive Polling Interval Endpoint 7 */
+ };
+ __I uint16_t RESERVED34[195];
+ __IO uint16_t RQPKTCOUNT1; /*!< USB Request Packet Count in Block Transfer Endpoint 1 */
+ __I uint16_t RESERVED35;
+ __IO uint16_t RQPKTCOUNT2; /*!< USB Request Packet Count in Block Transfer Endpoint 2 */
+ __I uint16_t RESERVED36;
+ __IO uint16_t RQPKTCOUNT3; /*!< USB Request Packet Count in Block Transfer Endpoint 3 */
+ __I uint16_t RESERVED37;
+ __IO uint16_t RQPKTCOUNT4; /*!< USB Request Packet Count in Block Transfer Endpoint 4 */
+ __I uint16_t RESERVED38;
+ __IO uint16_t RQPKTCOUNT5; /*!< USB Request Packet Count in Block Transfer Endpoint 5 */
+ __I uint16_t RESERVED39;
+ __IO uint16_t RQPKTCOUNT6; /*!< USB Request Packet Count in Block Transfer Endpoint 6 */
+ __I uint16_t RESERVED40;
+ __IO uint16_t RQPKTCOUNT7; /*!< USB Request Packet Count in Block Transfer Endpoint 7 */
+ __I uint16_t RESERVED41[17];
+ __IO uint16_t RXDPKTBUFDIS; /*!< USB Receive Double Packet Buffer Disable */
+ __IO uint16_t TXDPKTBUFDIS; /*!< USB Transmit Double Packet Buffer Disable */
+ __I uint32_t RESERVED42[47];
+ __IO uint32_t EPC; /*!< USB External Power Control */
+ __IO uint32_t EPCRIS; /*!< USB External Power Control Raw Interrupt Status */
+ __IO uint32_t EPCIM; /*!< USB External Power Control Interrupt Mask */
+ __IO uint32_t EPCISC; /*!< USB External Power Control Interrupt Status and Clear */
+ __IO uint32_t DRRIS; /*!< USB Device RESUME Raw Interrupt Status */
+ __IO uint32_t DRIM; /*!< USB Device RESUME Interrupt Mask */
+ __O uint32_t DRISC; /*!< USB Device RESUME Interrupt Status and Clear */
+ __IO uint32_t GPCS; /*!< USB General-Purpose Control and Status */
+ __I uint32_t RESERVED43[4];
+ __IO uint32_t VDC; /*!< USB VBUS Droop Control */
+ __IO uint32_t VDCRIS; /*!< USB VBUS Droop Control Raw Interrupt Status */
+ __IO uint32_t VDCIM; /*!< USB VBUS Droop Control Interrupt Mask */
+ __IO uint32_t VDCISC; /*!< USB VBUS Droop Control Interrupt Status and Clear */
+ __I uint32_t RESERVED44;
+ __IO uint32_t IDVRIS; /*!< USB ID Valid Detect Raw Interrupt Status */
+ __IO uint32_t IDVIM; /*!< USB ID Valid Detect Interrupt Mask */
+ __IO uint32_t IDVISC; /*!< USB ID Valid Detect Interrupt Status and Clear */
+ __IO uint32_t DMASEL; /*!< USB DMA Select */
+ __I uint32_t RESERVED45[731];
+ __IO uint32_t PP; /*!< USB Peripheral Properties */
+} USB0_Type;
+
+
+/* ================================================================================ */
+/* ================ EEPROM ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for EEPROM peripheral (EEPROM)
+ */
+
+typedef struct { /*!< EEPROM Structure */
+ __IO uint32_t EESIZE; /*!< EEPROM Size Information */
+ __IO uint32_t EEBLOCK; /*!< EEPROM Current Block */
+ __IO uint32_t EEOFFSET; /*!< EEPROM Current Offset */
+ __I uint32_t RESERVED0;
+ __IO uint32_t EERDWR; /*!< EEPROM Read-Write */
+ __IO uint32_t EERDWRINC; /*!< EEPROM Read-Write with Increment */
+ __IO uint32_t EEDONE; /*!< EEPROM Done Status */
+ __IO uint32_t EESUPP; /*!< EEPROM Support Control and Status */
+ __IO uint32_t EEUNLOCK; /*!< EEPROM Unlock */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t EEPROT; /*!< EEPROM Protection */
+ __IO uint32_t EEPASS0; /*!< EEPROM Password */
+ __IO uint32_t EEPASS1; /*!< EEPROM Password */
+ __IO uint32_t EEPASS2; /*!< EEPROM Password */
+ __IO uint32_t EEINT; /*!< EEPROM Interrupt */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t EEHIDE; /*!< EEPROM Block Hide */
+ __I uint32_t RESERVED3[11];
+ __IO uint32_t EEDBGME; /*!< EEPROM Debug Mass Erase */
+ __I uint32_t RESERVED4[975];
+ __IO uint32_t PP; /*!< EEPROM Peripheral Properties */
+} EEPROM_Type;
+
+
+/* ================================================================================ */
+/* ================ SYSEXC ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for SYSEXC peripheral (SYSEXC)
+ */
+
+typedef struct { /*!< SYSEXC Structure */
+ __IO uint32_t RIS; /*!< System Exception Raw Interrupt Status */
+ __IO uint32_t IM; /*!< System Exception Interrupt Mask */
+ __IO uint32_t MIS; /*!< System Exception Masked Interrupt Status */
+ __O uint32_t IC; /*!< System Exception Interrupt Clear */
+} SYSEXC_Type;
+
+
+/* ================================================================================ */
+/* ================ HIB ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for HIB peripheral (HIB)
+ */
+
+typedef struct { /*!< HIB Structure */
+ __IO uint32_t RTCC; /*!< Hibernation RTC Counter */
+ __IO uint32_t RTCM0; /*!< Hibernation RTC Match 0 */
+ __I uint32_t RESERVED0;
+ __IO uint32_t RTCLD; /*!< Hibernation RTC Load */
+ __IO uint32_t CTL; /*!< Hibernation Control */
+ __IO uint32_t IM; /*!< Hibernation Interrupt Mask */
+ __IO uint32_t RIS; /*!< Hibernation Raw Interrupt Status */
+ __IO uint32_t MIS; /*!< Hibernation Masked Interrupt Status */
+ __IO uint32_t IC; /*!< Hibernation Interrupt Clear */
+ __IO uint32_t RTCT; /*!< Hibernation RTC Trim */
+ __IO uint32_t RTCSS; /*!< Hibernation RTC Sub Seconds */
+ __I uint32_t RESERVED1;
+ __IO uint32_t DATA; /*!< Hibernation Data */
+} HIB_Type;
+
+
+/* ================================================================================ */
+/* ================ FLASH_CTRL ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for FLASH_CTRL peripheral (FLASH_CTRL)
+ */
+
+typedef struct { /*!< FLASH_CTRL Structure */
+ __IO uint32_t FMA; /*!< Flash Memory Address */
+ __IO uint32_t FMD; /*!< Flash Memory Data */
+ __IO uint32_t FMC; /*!< Flash Memory Control */
+ __IO uint32_t FCRIS; /*!< Flash Controller Raw Interrupt Status */
+ __IO uint32_t FCIM; /*!< Flash Controller Interrupt Mask */
+ __IO uint32_t FCMISC; /*!< Flash Controller Masked Interrupt Status and Clear */
+ __I uint32_t RESERVED0[2];
+ __IO uint32_t FMC2; /*!< Flash Memory Control 2 */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FWBVAL; /*!< Flash Write Buffer Valid */
+ __I uint32_t RESERVED2[51];
+ __IO uint32_t FWBN; /*!< Flash Write Buffer n */
+ __I uint32_t RESERVED3[943];
+ __IO uint32_t FSIZE; /*!< Flash Size */
+ __IO uint32_t SSIZE; /*!< SRAM Size */
+ __I uint32_t RESERVED4;
+
+ union {
+ __IO uint32_t ROMSWMAP_FLASH_CTRL_ALT; /*!< ROM Software Map */
+ __IO uint32_t ROMSWMAP; /*!< ROM Software Map */
+ };
+ __I uint32_t RESERVED5[72];
+ __IO uint32_t RMCTL; /*!< ROM Control */
+ __I uint32_t RESERVED6[55];
+ __IO uint32_t BOOTCFG; /*!< Boot Configuration */
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t USERREG0; /*!< User Register 0 */
+ __IO uint32_t USERREG1; /*!< User Register 1 */
+ __IO uint32_t USERREG2; /*!< User Register 2 */
+ __IO uint32_t USERREG3; /*!< User Register 3 */
+ __I uint32_t RESERVED8[4];
+ __IO uint32_t FMPRE0; /*!< Flash Memory Protection Read Enable 0 */
+ __IO uint32_t FMPRE1; /*!< Flash Memory Protection Read Enable 1 */
+ __IO uint32_t FMPRE2; /*!< Flash Memory Protection Read Enable 2 */
+ __IO uint32_t FMPRE3; /*!< Flash Memory Protection Read Enable 3 */
+ __I uint32_t RESERVED9[124];
+ __IO uint32_t FMPPE0; /*!< Flash Memory Protection Program Enable 0 */
+ __IO uint32_t FMPPE1; /*!< Flash Memory Protection Program Enable 1 */
+ __IO uint32_t FMPPE2; /*!< Flash Memory Protection Program Enable 2 */
+ __IO uint32_t FMPPE3; /*!< Flash Memory Protection Program Enable 3 */
+} FLASH_CTRL_Type;
+
+
+/* ================================================================================ */
+/* ================ SYSCTL ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for SYSCTL peripheral (SYSCTL)
+ */
+
+typedef struct { /*!< SYSCTL Structure */
+ __IO uint32_t DID0; /*!< Device Identification 0 */
+ __IO uint32_t DID1; /*!< Device Identification 1 */
+ __IO uint32_t DC0; /*!< Device Capabilities 0 */
+ __I uint32_t RESERVED0;
+ __IO uint32_t DC1; /*!< Device Capabilities 1 */
+ __IO uint32_t DC2; /*!< Device Capabilities 2 */
+ __IO uint32_t DC3; /*!< Device Capabilities 3 */
+ __IO uint32_t DC4; /*!< Device Capabilities 4 */
+ __IO uint32_t DC5; /*!< Device Capabilities 5 */
+ __IO uint32_t DC6; /*!< Device Capabilities 6 */
+ __IO uint32_t DC7; /*!< Device Capabilities 7 */
+ __IO uint32_t DC8; /*!< Device Capabilities 8 */
+ __IO uint32_t PBORCTL; /*!< Brown-Out Reset Control */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t SRCR0; /*!< Software Reset Control 0 */
+ __IO uint32_t SRCR1; /*!< Software Reset Control 1 */
+ __IO uint32_t SRCR2; /*!< Software Reset Control 2 */
+ __I uint32_t RESERVED2;
+ __IO uint32_t RIS; /*!< Raw Interrupt Status */
+ __IO uint32_t IMC; /*!< Interrupt Mask Control */
+ __IO uint32_t MISC; /*!< Masked Interrupt Status and Clear */
+ __IO uint32_t RESC; /*!< Reset Cause */
+ __IO uint32_t RCC; /*!< Run-Mode Clock Configuration */
+ __I uint32_t RESERVED3[2];
+ __IO uint32_t GPIOHBCTL; /*!< GPIO High-Performance Bus Control */
+ __IO uint32_t RCC2; /*!< Run-Mode Clock Configuration 2 */
+ __I uint32_t RESERVED4[2];
+ __IO uint32_t MOSCCTL; /*!< Main Oscillator Control */
+ __I uint32_t RESERVED5[32];
+ __IO uint32_t RCGC0; /*!< Run Mode Clock Gating Control Register 0 */
+ __IO uint32_t RCGC1; /*!< Run Mode Clock Gating Control Register 1 */
+ __IO uint32_t RCGC2; /*!< Run Mode Clock Gating Control Register 2 */
+ __I uint32_t RESERVED6;
+ __IO uint32_t SCGC0; /*!< Sleep Mode Clock Gating Control Register 0 */
+ __IO uint32_t SCGC1; /*!< Sleep Mode Clock Gating Control Register 1 */
+ __IO uint32_t SCGC2; /*!< Sleep Mode Clock Gating Control Register 2 */
+ __I uint32_t RESERVED7;
+ __IO uint32_t DCGC0; /*!< Deep Sleep Mode Clock Gating Control Register 0 */
+ __IO uint32_t DCGC1; /*!< Deep-Sleep Mode Clock Gating Control Register 1 */
+ __IO uint32_t DCGC2; /*!< Deep Sleep Mode Clock Gating Control Register 2 */
+ __I uint32_t RESERVED8[6];
+ __IO uint32_t DSLPCLKCFG; /*!< Deep Sleep Clock Configuration */
+ __I uint32_t RESERVED9;
+ __IO uint32_t SYSPROP; /*!< System Properties */
+ __IO uint32_t PIOSCCAL; /*!< Precision Internal Oscillator Calibration */
+ __IO uint32_t PIOSCSTAT; /*!< Precision Internal Oscillator Statistics */
+ __I uint32_t RESERVED10[2];
+ __IO uint32_t PLLFREQ0; /*!< PLL Frequency 0 */
+ __IO uint32_t PLLFREQ1; /*!< PLL Frequency 1 */
+ __IO uint32_t PLLSTAT; /*!< PLL Status */
+ __I uint32_t RESERVED11[7];
+ __IO uint32_t SLPPWRCFG; /*!< Sleep Power Configuration */
+ __IO uint32_t DSLPPWRCFG; /*!< Deep-Sleep Power Configuration */
+ __IO uint32_t DC9; /*!< Device Capabilities 9 */
+ __I uint32_t RESERVED12[3];
+ __IO uint32_t NVMSTAT; /*!< Non-Volatile Memory Information */
+ __I uint32_t RESERVED13[4];
+ __IO uint32_t LDOSPCTL; /*!< LDO Sleep Power Control */
+ __I uint32_t RESERVED14;
+ __IO uint32_t LDODPCTL; /*!< LDO Deep-Sleep Power Control */
+ __I uint32_t RESERVED15[80];
+ __IO uint32_t PPWD; /*!< Watchdog Timer Peripheral Present */
+ __IO uint32_t PPTIMER; /*!< 16/32-Bit General-Purpose Timer Peripheral Present */
+ __IO uint32_t PPGPIO; /*!< General-Purpose Input/Output Peripheral Present */
+ __IO uint32_t PPDMA; /*!< Micro Direct Memory Access Peripheral Present */
+ __I uint32_t RESERVED16;
+ __IO uint32_t PPHIB; /*!< Hibernation Peripheral Present */
+ __IO uint32_t PPUART; /*!< Universal Asynchronous Receiver/Transmitter Peripheral Present */
+ __IO uint32_t PPSSI; /*!< Synchronous Serial Interface Peripheral Present */
+ __IO uint32_t PPI2C; /*!< Inter-Integrated Circuit Peripheral Present */
+ __I uint32_t RESERVED17;
+ __IO uint32_t PPUSB; /*!< Universal Serial Bus Peripheral Present */
+ __I uint32_t RESERVED18[2];
+ __IO uint32_t PPCAN; /*!< Controller Area Network Peripheral Present */
+ __IO uint32_t PPADC; /*!< Analog-to-Digital Converter Peripheral Present */
+ __IO uint32_t PPACMP; /*!< Analog Comparator Peripheral Present */
+ __IO uint32_t PPPWM; /*!< Pulse Width Modulator Peripheral Present */
+ __IO uint32_t PPQEI; /*!< Quadrature Encoder Interface Peripheral Present */
+ __I uint32_t RESERVED19[4];
+ __IO uint32_t PPEEPROM; /*!< EEPROM Peripheral Present */
+ __IO uint32_t PPWTIMER; /*!< 32/64-Bit Wide General-Purpose Timer Peripheral Present */
+ __I uint32_t RESERVED20[104];
+ __IO uint32_t SRWD; /*!< Watchdog Timer Software Reset */
+ __IO uint32_t SRTIMER; /*!< 16/32-Bit General-Purpose Timer Software Reset */
+ __IO uint32_t SRGPIO; /*!< General-Purpose Input/Output Software Reset */
+ __IO uint32_t SRDMA; /*!< Micro Direct Memory Access Software Reset */
+ __I uint32_t RESERVED21;
+ __IO uint32_t SRHIB; /*!< Hibernation Software Reset */
+ __IO uint32_t SRUART; /*!< Universal Asynchronous Receiver/Transmitter Software Reset */
+ __IO uint32_t SRSSI; /*!< Synchronous Serial Interface Software Reset */
+ __IO uint32_t SRI2C; /*!< Inter-Integrated Circuit Software Reset */
+ __I uint32_t RESERVED22;
+ __IO uint32_t SRUSB; /*!< Universal Serial Bus Software Reset */
+ __I uint32_t RESERVED23[2];
+ __IO uint32_t SRCAN; /*!< Controller Area Network Software Reset */
+ __IO uint32_t SRADC; /*!< Analog-to-Digital Converter Software Reset */
+ __IO uint32_t SRACMP; /*!< Analog Comparator Software Reset */
+ __IO uint32_t SRPWM; /*!< Pulse Width Modulator Software Reset */
+ __IO uint32_t SRQEI; /*!< Quadrature Encoder Interface Software Reset */
+ __I uint32_t RESERVED24[4];
+ __IO uint32_t SREEPROM; /*!< EEPROM Software Reset */
+ __IO uint32_t SRWTIMER; /*!< 32/64-Bit Wide General-Purpose Timer Software Reset */
+ __I uint32_t RESERVED25[40];
+ __IO uint32_t RCGCWD; /*!< Watchdog Timer Run Mode Clock Gating Control */
+ __IO uint32_t RCGCTIMER; /*!< 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control */
+ __IO uint32_t RCGCGPIO; /*!< General-Purpose Input/Output Run Mode Clock Gating Control */
+ __IO uint32_t RCGCDMA; /*!< Micro Direct Memory Access Run Mode Clock Gating Control */
+ __I uint32_t RESERVED26;
+ __IO uint32_t RCGCHIB; /*!< Hibernation Run Mode Clock Gating Control */
+ __IO uint32_t RCGCUART; /*!< Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating
+ Control */
+ __IO uint32_t RCGCSSI; /*!< Synchronous Serial Interface Run Mode Clock Gating Control */
+ __IO uint32_t RCGCI2C; /*!< Inter-Integrated Circuit Run Mode Clock Gating Control */
+ __I uint32_t RESERVED27;
+ __IO uint32_t RCGCUSB; /*!< Universal Serial Bus Run Mode Clock Gating Control */
+ __I uint32_t RESERVED28[2];
+ __IO uint32_t RCGCCAN; /*!< Controller Area Network Run Mode Clock Gating Control */
+ __IO uint32_t RCGCADC; /*!< Analog-to-Digital Converter Run Mode Clock Gating Control */
+ __IO uint32_t RCGCACMP; /*!< Analog Comparator Run Mode Clock Gating Control */
+ __IO uint32_t RCGCPWM; /*!< Pulse Width Modulator Run Mode Clock Gating Control */
+ __IO uint32_t RCGCQEI; /*!< Quadrature Encoder Interface Run Mode Clock Gating Control */
+ __I uint32_t RESERVED29[4];
+ __IO uint32_t RCGCEEPROM; /*!< EEPROM Run Mode Clock Gating Control */
+ __IO uint32_t RCGCWTIMER; /*!< 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control */
+ __I uint32_t RESERVED30[40];
+ __IO uint32_t SCGCWD; /*!< Watchdog Timer Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCTIMER; /*!< 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCGPIO; /*!< General-Purpose Input/Output Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCDMA; /*!< Micro Direct Memory Access Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED31;
+ __IO uint32_t SCGCHIB; /*!< Hibernation Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCUART; /*!< Universal Asynchronous Receiver/Transmitter Sleep Mode Clock
+ Gating Control */
+ __IO uint32_t SCGCSSI; /*!< Synchronous Serial Interface Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCI2C; /*!< Inter-Integrated Circuit Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED32;
+ __IO uint32_t SCGCUSB; /*!< Universal Serial Bus Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED33[2];
+ __IO uint32_t SCGCCAN; /*!< Controller Area Network Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCADC; /*!< Analog-to-Digital Converter Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCACMP; /*!< Analog Comparator Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCPWM; /*!< Pulse Width Modulator Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCQEI; /*!< Quadrature Encoder Interface Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED34[4];
+ __IO uint32_t SCGCEEPROM; /*!< EEPROM Sleep Mode Clock Gating Control */
+ __IO uint32_t SCGCWTIMER; /*!< 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating
+ Control */
+ __I uint32_t RESERVED35[40];
+ __IO uint32_t DCGCWD; /*!< Watchdog Timer Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCTIMER; /*!< 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating
+ Control */
+ __IO uint32_t DCGCGPIO; /*!< General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCDMA; /*!< Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED36;
+ __IO uint32_t DCGCHIB; /*!< Hibernation Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCUART; /*!< Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode
+ Clock Gating Control */
+ __IO uint32_t DCGCSSI; /*!< Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCI2C; /*!< Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED37;
+ __IO uint32_t DCGCUSB; /*!< Universal Serial Bus Deep-Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED38[2];
+ __IO uint32_t DCGCCAN; /*!< Controller Area Network Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCADC; /*!< Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCACMP; /*!< Analog Comparator Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCPWM; /*!< Pulse Width Modulator Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCQEI; /*!< Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control */
+ __I uint32_t RESERVED39[4];
+ __IO uint32_t DCGCEEPROM; /*!< EEPROM Deep-Sleep Mode Clock Gating Control */
+ __IO uint32_t DCGCWTIMER; /*!< 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating
+ Control */
+ __I uint32_t RESERVED40[104];
+ __IO uint32_t PRWD; /*!< Watchdog Timer Peripheral Ready */
+ __IO uint32_t PRTIMER; /*!< 16/32-Bit General-Purpose Timer Peripheral Ready */
+ __IO uint32_t PRGPIO; /*!< General-Purpose Input/Output Peripheral Ready */
+ __IO uint32_t PRDMA; /*!< Micro Direct Memory Access Peripheral Ready */
+ __I uint32_t RESERVED41;
+ __IO uint32_t PRHIB; /*!< Hibernation Peripheral Ready */
+ __IO uint32_t PRUART; /*!< Universal Asynchronous Receiver/Transmitter Peripheral Ready */
+ __IO uint32_t PRSSI; /*!< Synchronous Serial Interface Peripheral Ready */
+ __IO uint32_t PRI2C; /*!< Inter-Integrated Circuit Peripheral Ready */
+ __I uint32_t RESERVED42;
+ __IO uint32_t PRUSB; /*!< Universal Serial Bus Peripheral Ready */
+ __I uint32_t RESERVED43[2];
+ __IO uint32_t PRCAN; /*!< Controller Area Network Peripheral Ready */
+ __IO uint32_t PRADC; /*!< Analog-to-Digital Converter Peripheral Ready */
+ __IO uint32_t PRACMP; /*!< Analog Comparator Peripheral Ready */
+ __IO uint32_t PRPWM; /*!< Pulse Width Modulator Peripheral Ready */
+ __IO uint32_t PRQEI; /*!< Quadrature Encoder Interface Peripheral Ready */
+ __I uint32_t RESERVED44[4];
+ __IO uint32_t PREEPROM; /*!< EEPROM Peripheral Ready */
+ __IO uint32_t PRWTIMER; /*!< 32/64-Bit Wide General-Purpose Timer Peripheral Ready */
+} SYSCTL_Type;
+
+
+/* ================================================================================ */
+/* ================ UDMA ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief Register map for UDMA peripheral (UDMA)
+ */
+
+typedef struct { /*!< UDMA Structure */
+ __IO uint32_t STAT; /*!< DMA Status */
+ __O uint32_t CFG; /*!< DMA Configuration */
+ __IO uint32_t CTLBASE; /*!< DMA Channel Control Base Pointer */
+ __IO uint32_t ALTBASE; /*!< DMA Alternate Channel Control Base Pointer */
+ __IO uint32_t WAITSTAT; /*!< DMA Channel Wait-on-Request Status */
+ __O uint32_t SWREQ; /*!< DMA Channel Software Request */
+ __IO uint32_t USEBURSTSET; /*!< DMA Channel Useburst Set */
+ __O uint32_t USEBURSTCLR; /*!< DMA Channel Useburst Clear */
+ __IO uint32_t REQMASKSET; /*!< DMA Channel Request Mask Set */
+ __O uint32_t REQMASKCLR; /*!< DMA Channel Request Mask Clear */
+ __IO uint32_t ENASET; /*!< DMA Channel Enable Set */
+ __O uint32_t ENACLR; /*!< DMA Channel Enable Clear */
+ __IO uint32_t ALTSET; /*!< DMA Channel Primary Alternate Set */
+ __O uint32_t ALTCLR; /*!< DMA Channel Primary Alternate Clear */
+ __IO uint32_t PRIOSET; /*!< DMA Channel Priority Set */
+ __O uint32_t PRIOCLR; /*!< DMA Channel Priority Clear */
+ __I uint32_t RESERVED0[3];
+ __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear */
+ __I uint32_t RESERVED1[300];
+ __IO uint32_t CHASGN; /*!< DMA Channel Assignment */
+ __IO uint32_t CHIS; /*!< DMA Channel Interrupt Status */
+ __I uint32_t RESERVED2[2];
+ __IO uint32_t CHMAP0; /*!< DMA Channel Map Select 0 */
+ __IO uint32_t CHMAP1; /*!< DMA Channel Map Select 1 */
+ __IO uint32_t CHMAP2; /*!< DMA Channel Map Select 2 */
+ __IO uint32_t CHMAP3; /*!< DMA Channel Map Select 3 */
+} UDMA_Type;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ /* anonymous unions are enabled by default */
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+
+#define WATCHDOG0_BASE 0x40000000UL
+#define WATCHDOG1_BASE 0x40001000UL
+#define GPIOA_BASE 0x40004000UL
+#define GPIOB_BASE 0x40005000UL
+#define GPIOC_BASE 0x40006000UL
+#define GPIOD_BASE 0x40007000UL
+#define SSI0_BASE 0x40008000UL
+#define SSI1_BASE 0x40009000UL
+#define SSI2_BASE 0x4000A000UL
+#define SSI3_BASE 0x4000B000UL
+#define UART0_BASE 0x4000C000UL
+#define UART1_BASE 0x4000D000UL
+#define UART2_BASE 0x4000E000UL
+#define UART3_BASE 0x4000F000UL
+#define UART4_BASE 0x40010000UL
+#define UART5_BASE 0x40011000UL
+#define UART6_BASE 0x40012000UL
+#define UART7_BASE 0x40013000UL
+#define I2C0_BASE 0x40020000UL
+#define I2C1_BASE 0x40021000UL
+#define I2C2_BASE 0x40022000UL
+#define I2C3_BASE 0x40023000UL
+#define GPIOE_BASE 0x40024000UL
+#define GPIOF_BASE 0x40025000UL
+#define PWM0_BASE 0x40028000UL
+#define PWM1_BASE 0x40029000UL
+#define QEI0_BASE 0x4002C000UL
+#define QEI1_BASE 0x4002D000UL
+#define TIMER0_BASE 0x40030000UL
+#define TIMER1_BASE 0x40031000UL
+#define TIMER2_BASE 0x40032000UL
+#define TIMER3_BASE 0x40033000UL
+#define TIMER4_BASE 0x40034000UL
+#define TIMER5_BASE 0x40035000UL
+#define WTIMER0_BASE 0x40036000UL
+#define WTIMER1_BASE 0x40037000UL
+#define ADC0_BASE 0x40038000UL
+#define ADC1_BASE 0x40039000UL
+#define COMP_BASE 0x4003C000UL
+#define CAN0_BASE 0x40040000UL
+#define CAN1_BASE 0x40041000UL
+#define WTIMER2_BASE 0x4004C000UL
+#define WTIMER3_BASE 0x4004D000UL
+#define WTIMER4_BASE 0x4004E000UL
+#define WTIMER5_BASE 0x4004F000UL
+#define USB0_BASE 0x40050000UL
+#define GPIOA_AHB_BASE 0x40058000UL
+#define GPIOB_AHB_BASE 0x40059000UL
+#define GPIOC_AHB_BASE 0x4005A000UL
+#define GPIOD_AHB_BASE 0x4005B000UL
+#define GPIOE_AHB_BASE 0x4005C000UL
+#define GPIOF_AHB_BASE 0x4005D000UL
+#define EEPROM_BASE 0x400AF000UL
+#define SYSEXC_BASE 0x400F9000UL
+#define HIB_BASE 0x400FC000UL
+#define FLASH_CTRL_BASE 0x400FD000UL
+#define SYSCTL_BASE 0x400FE000UL
+#define UDMA_BASE 0x400FF000UL
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+
+#define WATCHDOG0 ((WATCHDOG0_Type *) WATCHDOG0_BASE)
+#define WATCHDOG1 ((WATCHDOG0_Type *) WATCHDOG1_BASE)
+#define GPIOA ((GPIOA_Type *) GPIOA_BASE)
+#define GPIOB ((GPIOA_Type *) GPIOB_BASE)
+#define GPIOC ((GPIOA_Type *) GPIOC_BASE)
+#define GPIOD ((GPIOA_Type *) GPIOD_BASE)
+#define SSI0 ((SSI0_Type *) SSI0_BASE)
+#define SSI1 ((SSI0_Type *) SSI1_BASE)
+#define SSI2 ((SSI0_Type *) SSI2_BASE)
+#define SSI3 ((SSI0_Type *) SSI3_BASE)
+#define UART0 ((UART0_Type *) UART0_BASE)
+#define UART1 ((UART0_Type *) UART1_BASE)
+#define UART2 ((UART0_Type *) UART2_BASE)
+#define UART3 ((UART0_Type *) UART3_BASE)
+#define UART4 ((UART0_Type *) UART4_BASE)
+#define UART5 ((UART0_Type *) UART5_BASE)
+#define UART6 ((UART0_Type *) UART6_BASE)
+#define UART7 ((UART0_Type *) UART7_BASE)
+#define I2C0 ((I2C0_Type *) I2C0_BASE)
+#define I2C1 ((I2C0_Type *) I2C1_BASE)
+#define I2C2 ((I2C0_Type *) I2C2_BASE)
+#define I2C3 ((I2C0_Type *) I2C3_BASE)
+#define GPIOE ((GPIOA_Type *) GPIOE_BASE)
+#define GPIOF ((GPIOA_Type *) GPIOF_BASE)
+#define PWM0 ((PWM0_Type *) PWM0_BASE)
+#define PWM1 ((PWM0_Type *) PWM1_BASE)
+#define QEI0 ((QEI0_Type *) QEI0_BASE)
+#define QEI1 ((QEI0_Type *) QEI1_BASE)
+#define TIMER0 ((TIMER0_Type *) TIMER0_BASE)
+#define TIMER1 ((TIMER0_Type *) TIMER1_BASE)
+#define TIMER2 ((TIMER0_Type *) TIMER2_BASE)
+#define TIMER3 ((TIMER0_Type *) TIMER3_BASE)
+#define TIMER4 ((TIMER0_Type *) TIMER4_BASE)
+#define TIMER5 ((TIMER0_Type *) TIMER5_BASE)
+#define WTIMER0 ((WTIMER0_Type *) WTIMER0_BASE)
+#define WTIMER1 ((TIMER0_Type *) WTIMER1_BASE)
+#define ADC0 ((ADC0_Type *) ADC0_BASE)
+#define ADC1 ((ADC0_Type *) ADC1_BASE)
+#define COMP ((COMP_Type *) COMP_BASE)
+#define CAN0 ((CAN0_Type *) CAN0_BASE)
+#define CAN1 ((CAN0_Type *) CAN1_BASE)
+#define WTIMER2 ((TIMER0_Type *) WTIMER2_BASE)
+#define WTIMER3 ((TIMER0_Type *) WTIMER3_BASE)
+#define WTIMER4 ((TIMER0_Type *) WTIMER4_BASE)
+#define WTIMER5 ((TIMER0_Type *) WTIMER5_BASE)
+#define USB0 ((USB0_Type *) USB0_BASE)
+#define GPIOA_AHB ((GPIOA_Type *) GPIOA_AHB_BASE)
+#define GPIOB_AHB ((GPIOA_Type *) GPIOB_AHB_BASE)
+#define GPIOC_AHB ((GPIOA_Type *) GPIOC_AHB_BASE)
+#define GPIOD_AHB ((GPIOA_Type *) GPIOD_AHB_BASE)
+#define GPIOE_AHB ((GPIOA_Type *) GPIOE_AHB_BASE)
+#define GPIOF_AHB ((GPIOA_Type *) GPIOF_AHB_BASE)
+#define EEPROM ((EEPROM_Type *) EEPROM_BASE)
+#define SYSEXC ((SYSEXC_Type *) SYSEXC_BASE)
+#define HIB ((HIB_Type *) HIB_BASE)
+#define FLASH_CTRL ((FLASH_CTRL_Type *) FLASH_CTRL_BASE)
+#define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE)
+#define UDMA ((UDMA_Type *) UDMA_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group TM4C123GH6PM */
+/** @} */ /* End of group Texas Instruments */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* TM4C123GH6PM_H */
+
diff --git a/lesson-17/ek-tm4c123gxl/cmsis_armclang.h b/lesson-17/ek-tm4c123gxl/cmsis_armclang.h
new file mode 100644
index 0000000..6911417
--- /dev/null
+++ b/lesson-17/ek-tm4c123gxl/cmsis_armclang.h
@@ -0,0 +1,1503 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.4.3
+ * @date 27. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#ifndef __STACK_SEAL
+#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
+#endif
+
+#ifndef __TZ_STACK_SEAL_SIZE
+#define __TZ_STACK_SEAL_SIZE 8U
+#endif
+
+#ifndef __TZ_STACK_SEAL_VALUE
+#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
+#endif
+
+
+__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
+ *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
+}
+#endif
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+#endif
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
+ Can only be executed in Privileged modes.
+ */
+#ifndef __ARM_COMPAT_H
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+#endif
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+ __ISB();
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define __SADD8 __builtin_arm_sadd8
+#define __QADD8 __builtin_arm_qadd8
+#define __SHADD8 __builtin_arm_shadd8
+#define __UADD8 __builtin_arm_uadd8
+#define __UQADD8 __builtin_arm_uqadd8
+#define __UHADD8 __builtin_arm_uhadd8
+#define __SSUB8 __builtin_arm_ssub8
+#define __QSUB8 __builtin_arm_qsub8
+#define __SHSUB8 __builtin_arm_shsub8
+#define __USUB8 __builtin_arm_usub8
+#define __UQSUB8 __builtin_arm_uqsub8
+#define __UHSUB8 __builtin_arm_uhsub8
+#define __SADD16 __builtin_arm_sadd16
+#define __QADD16 __builtin_arm_qadd16
+#define __SHADD16 __builtin_arm_shadd16
+#define __UADD16 __builtin_arm_uadd16
+#define __UQADD16 __builtin_arm_uqadd16
+#define __UHADD16 __builtin_arm_uhadd16
+#define __SSUB16 __builtin_arm_ssub16
+#define __QSUB16 __builtin_arm_qsub16
+#define __SHSUB16 __builtin_arm_shsub16
+#define __USUB16 __builtin_arm_usub16
+#define __UQSUB16 __builtin_arm_uqsub16
+#define __UHSUB16 __builtin_arm_uhsub16
+#define __SASX __builtin_arm_sasx
+#define __QASX __builtin_arm_qasx
+#define __SHASX __builtin_arm_shasx
+#define __UASX __builtin_arm_uasx
+#define __UQASX __builtin_arm_uqasx
+#define __UHASX __builtin_arm_uhasx
+#define __SSAX __builtin_arm_ssax
+#define __QSAX __builtin_arm_qsax
+#define __SHSAX __builtin_arm_shsax
+#define __USAX __builtin_arm_usax
+#define __UQSAX __builtin_arm_uqsax
+#define __UHSAX __builtin_arm_uhsax
+#define __USAD8 __builtin_arm_usad8
+#define __USADA8 __builtin_arm_usada8
+#define __SSAT16 __builtin_arm_ssat16
+#define __USAT16 __builtin_arm_usat16
+#define __UXTB16 __builtin_arm_uxtb16
+#define __UXTAB16 __builtin_arm_uxtab16
+#define __SXTB16 __builtin_arm_sxtb16
+#define __SXTAB16 __builtin_arm_sxtab16
+#define __SMUAD __builtin_arm_smuad
+#define __SMUADX __builtin_arm_smuadx
+#define __SMLAD __builtin_arm_smlad
+#define __SMLADX __builtin_arm_smladx
+#define __SMLALD __builtin_arm_smlald
+#define __SMLALDX __builtin_arm_smlaldx
+#define __SMUSD __builtin_arm_smusd
+#define __SMUSDX __builtin_arm_smusdx
+#define __SMLSD __builtin_arm_smlsd
+#define __SMLSDX __builtin_arm_smlsdx
+#define __SMLSLD __builtin_arm_smlsld
+#define __SMLSLDX __builtin_arm_smlsldx
+#define __SEL __builtin_arm_sel
+#define __QADD __builtin_arm_qadd
+#define __QSUB __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/lesson-17/ek-tm4c123gxl/core_cm4.h b/lesson-17/ek-tm4c123gxl/core_cm4.h
new file mode 100644
index 0000000..e21cd14
--- /dev/null
+++ b/lesson-17/ek-tm4c123gxl/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.1.2
+ * @date 04. June 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */